
Mujtaba M. Chaudry
Examiner (ID: 16088, Phone: (571)272-3817 , Office: P/2112 )
| Most Active Art Unit | 2112 |
| Art Unit(s) | 2112, 2133 |
| Total Applications | 1571 |
| Issued Applications | 1295 |
| Pending Applications | 106 |
| Abandoned Applications | 191 |
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|---|---|---|---|
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