Search

Muna A. Techane

Examiner (ID: 6002, Phone: (571)272-7856 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
804
Issued Applications
695
Pending Applications
83
Abandoned Applications
41

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18639280 [patent_doc_number] => 11763896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Preread and read threshold voltage optimization [patent_app_type] => utility [patent_app_number] => 17/951593 [patent_app_country] => US [patent_app_date] => 2022-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10435 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17951593 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/951593
Preread and read threshold voltage optimization Sep 22, 2022 Issued
Array ( [id] => 18689949 [patent_doc_number] => 11785710 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Module board and memory module including the same [patent_app_type] => utility [patent_app_number] => 17/947397 [patent_app_country] => US [patent_app_date] => 2022-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8764 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17947397 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/947397
Module board and memory module including the same Sep 18, 2022 Issued
Array ( [id] => 18623551 [patent_doc_number] => 11756604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Managing write disturb for units of memory in a memory sub-system using a randomized refresh period [patent_app_type] => utility [patent_app_number] => 17/946612 [patent_app_country] => US [patent_app_date] => 2022-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8241 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17946612 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/946612
Managing write disturb for units of memory in a memory sub-system using a randomized refresh period Sep 15, 2022 Issued
Array ( [id] => 18240156 [patent_doc_number] => 20230072467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => Method and System for Read Reference Voltage Calibration for Non-Volatile Memories [patent_app_type] => utility [patent_app_number] => 17/939718 [patent_app_country] => US [patent_app_date] => 2022-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12950 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17939718 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/939718
Method and system for read reference voltage calibration for non-volatile memories Sep 6, 2022 Issued
Array ( [id] => 18661054 [patent_doc_number] => 20230307067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => REFERENCE VOLTAGE GENERATING CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/903617 [patent_app_country] => US [patent_app_date] => 2022-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3740 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17903617 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/903617
Reference voltage generating circuit and semiconductor memory device Sep 5, 2022 Issued
Array ( [id] => 19022874 [patent_doc_number] => 20240079045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => OPTIMIZATION OF NON-ALIGNED HOST WRITES [patent_app_type] => utility [patent_app_number] => 17/903750 [patent_app_country] => US [patent_app_date] => 2022-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5706 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17903750 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/903750
Optimization of non-aligned host writes Sep 5, 2022 Issued
Array ( [id] => 19596783 [patent_doc_number] => 12154636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Anti-fuse structure, anti-fuse array and memory [patent_app_type] => utility [patent_app_number] => 17/929747 [patent_app_country] => US [patent_app_date] => 2022-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7663 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17929747 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/929747
Anti-fuse structure, anti-fuse array and memory Sep 4, 2022 Issued
Array ( [id] => 19596766 [patent_doc_number] => 12154619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Nonvolatile memory [patent_app_type] => utility [patent_app_number] => 17/929439 [patent_app_country] => US [patent_app_date] => 2022-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 27 [patent_no_of_words] => 18585 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17929439 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/929439
Nonvolatile memory Sep 1, 2022 Issued
Array ( [id] => 19670653 [patent_doc_number] => 12183420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Memory array with compensated word line access delay [patent_app_type] => utility [patent_app_number] => 17/899849 [patent_app_country] => US [patent_app_date] => 2022-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10761 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17899849 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/899849
Memory array with compensated word line access delay Aug 30, 2022 Issued
Array ( [id] => 18615520 [patent_doc_number] => 20230282257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/898981 [patent_app_country] => US [patent_app_date] => 2022-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16650 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17898981 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/898981
Memory system Aug 29, 2022 Issued
Array ( [id] => 18868055 [patent_doc_number] => 20230422492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME, MEMORY AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/899145 [patent_app_country] => US [patent_app_date] => 2022-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10848 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17899145 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/899145
Semiconductor structure and method for manufacturing same, memory and operation method thereof Aug 29, 2022 Issued
Array ( [id] => 19007478 [patent_doc_number] => 20240071549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR MODULE LEVEL ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 17/822909 [patent_app_country] => US [patent_app_date] => 2022-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18077 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17822909 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/822909
APPARATUSES, SYSTEMS, AND METHODS FOR MODULE LEVEL ERROR CORRECTION Aug 28, 2022 Pending
Array ( [id] => 18439707 [patent_doc_number] => 20230187002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => STORAGE CONTROLLER USING HISTORY DATA, METHOD OF OPERATING THE SAME, AND METHOD OF OPERATING STORAGE DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/893476 [patent_app_country] => US [patent_app_date] => 2022-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14458 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17893476 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/893476
Storage controller using history data, method of operating the same, and method of operating storage device including the same Aug 22, 2022 Issued
Array ( [id] => 19654238 [patent_doc_number] => 12176038 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Memory device and read operation during suspension of program operation thereof [patent_app_type] => utility [patent_app_number] => 17/891068 [patent_app_country] => US [patent_app_date] => 2022-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 22325 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17891068 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/891068
Memory device and read operation during suspension of program operation thereof Aug 17, 2022 Issued
Array ( [id] => 18833576 [patent_doc_number] => 20230402103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-14 [patent_title] => ADAPTIVE ERASE PULSE WIDTH MODULATION BASED ON ERASE SUSPEND DURING ERASE PULSE RAMPING PERIOD [patent_app_type] => utility [patent_app_number] => 17/887765 [patent_app_country] => US [patent_app_date] => 2022-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11853 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17887765 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/887765
Adaptive erase pulse width modulation based on erase suspend during erase pulse ramping period Aug 14, 2022 Issued
Array ( [id] => 19906328 [patent_doc_number] => 12283340 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Method for controlling sense amplifier and control device using the same [patent_app_type] => utility [patent_app_number] => 17/886423 [patent_app_country] => US [patent_app_date] => 2022-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17886423 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/886423
Method for controlling sense amplifier and control device using the same Aug 10, 2022 Issued
Array ( [id] => 18097032 [patent_doc_number] => 20220415373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => Computing-In-Memory Architecture [patent_app_type] => utility [patent_app_number] => 17/884650 [patent_app_country] => US [patent_app_date] => 2022-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3825 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884650 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/884650
Computing-in-memory architecture Aug 9, 2022 Issued
Array ( [id] => 19444276 [patent_doc_number] => 12094564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Memory device and computing method thereof [patent_app_type] => utility [patent_app_number] => 17/817701 [patent_app_country] => US [patent_app_date] => 2022-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 32 [patent_no_of_words] => 7615 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17817701 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/817701
Memory device and computing method thereof Aug 4, 2022 Issued
Array ( [id] => 18394558 [patent_doc_number] => 20230162779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => ELECTRONIC DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/881208 [patent_app_country] => US [patent_app_date] => 2022-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9050 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17881208 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/881208
Electronic device and operating method thereof Aug 3, 2022 Issued
Array ( [id] => 18723325 [patent_doc_number] => 11800703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Vertical fuse memory in one-time program memory cells [patent_app_type] => utility [patent_app_number] => 17/880754 [patent_app_country] => US [patent_app_date] => 2022-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 8559 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17880754 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/880754
Vertical fuse memory in one-time program memory cells Aug 3, 2022 Issued
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