Search

Muna A. Techane

Examiner (ID: 6002, Phone: (571)272-7856 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
804
Issued Applications
695
Pending Applications
83
Abandoned Applications
41

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20829391 [patent_doc_number] => 12682969 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-14 [patent_title] => One-time programmable (OTP) arrays with metal-semiconductor-metal (MSM) selectors for integrated circuitry [patent_app_type] => utility [patent_app_number] => 17/878796 [patent_app_country] => US [patent_app_date] => 2022-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 5461 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17878796 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/878796
One-time programmable (OTP) arrays with metal-semiconductor-metal (MSM) selectors for integrated circuitry Jul 31, 2022 Issued
Array ( [id] => 18351316 [patent_doc_number] => 20230139427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => OPERATION METHOD OF NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/878019 [patent_app_country] => US [patent_app_date] => 2022-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30101 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17878019 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/878019
Operation method of nonvolatile memory device Jul 30, 2022 Issued
Array ( [id] => 19341282 [patent_doc_number] => 12051477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Indicating a status of a memory built-in self-test for multiple memory device ranks [patent_app_type] => utility [patent_app_number] => 17/815747 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 20622 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815747 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/815747
Indicating a status of a memory built-in self-test for multiple memory device ranks Jul 27, 2022 Issued
Array ( [id] => 19277090 [patent_doc_number] => 12027221 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-02 [patent_title] => Integrated circuit device [patent_app_type] => utility [patent_app_number] => 17/815141 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 16262 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815141 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/815141
Integrated circuit device Jul 25, 2022 Issued
Array ( [id] => 19168273 [patent_doc_number] => 11984184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Voltage testing circuit with error protection scheme [patent_app_type] => utility [patent_app_number] => 17/873869 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6045 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873869 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/873869
Voltage testing circuit with error protection scheme Jul 25, 2022 Issued
Array ( [id] => 20161145 [patent_doc_number] => 12387778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Phase-to-phase mismatch reduction in a clock circuit of a memory device [patent_app_type] => utility [patent_app_number] => 17/813484 [patent_app_country] => US [patent_app_date] => 2022-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9756 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813484 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/813484
Phase-to-phase mismatch reduction in a clock circuit of a memory device Jul 18, 2022 Issued
Array ( [id] => 18905759 [patent_doc_number] => 20240021244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => MEMORY DEVICE FOR IN-MEMORY COMPUTING [patent_app_type] => utility [patent_app_number] => 17/812783 [patent_app_country] => US [patent_app_date] => 2022-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12678 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17812783 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/812783
Memory device for in-memory computing Jul 14, 2022 Issued
Array ( [id] => 19781301 [patent_doc_number] => 12230339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Electronic device and driving method thereof [patent_app_type] => utility [patent_app_number] => 18/036036 [patent_app_country] => US [patent_app_date] => 2022-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7752 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18036036 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/036036
Electronic device and driving method thereof Jul 11, 2022 Issued
Array ( [id] => 17963407 [patent_doc_number] => 20220343988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => STRUCTURES AND METHODS OF IDENTIFYING UNPROGRAMMED BITS FOR ONE-TIME-PROGRAMMABLE-MEMORY (OTPM) [patent_app_type] => utility [patent_app_number] => 17/860380 [patent_app_country] => US [patent_app_date] => 2022-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4411 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17860380 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/860380
Structures and methods of identifying unprogrammed bits for one-time-programmable-memory (OTPM) Jul 7, 2022 Issued
Array ( [id] => 19494102 [patent_doc_number] => 12112823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Method and system for repairing faulty cells of memory device [patent_app_type] => utility [patent_app_number] => 17/858745 [patent_app_country] => US [patent_app_date] => 2022-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 8276 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17858745 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/858745
Method and system for repairing faulty cells of memory device Jul 5, 2022 Issued
Array ( [id] => 18615531 [patent_doc_number] => 20230282268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => CIRCUIT FOR READING OUT DATA, METHOD FOR READING OUT DATA AND MEMORY [patent_app_type] => utility [patent_app_number] => 17/810596 [patent_app_country] => US [patent_app_date] => 2022-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8233 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17810596 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/810596
Circuit for reading out data, method for reading out data and memory Jul 1, 2022 Issued
Array ( [id] => 19596803 [patent_doc_number] => 12154656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Error pin training with graphics DDR memory [patent_app_type] => utility [patent_app_number] => 17/854213 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5766 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854213 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854213
Error pin training with graphics DDR memory Jun 29, 2022 Issued
Array ( [id] => 19679105 [patent_doc_number] => 12190976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Method and device for checking data, electronic device, and storage medium [patent_app_type] => utility [patent_app_number] => 17/854138 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10227 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854138 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854138
Method and device for checking data, electronic device, and storage medium Jun 29, 2022 Issued
Array ( [id] => 18882604 [patent_doc_number] => 20240005973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => Doped BiSb (012) or Undoped BiSb (001) Topological Insulator with GeNiFe Buffer Layer and/or Interlayer for SOT Based Sensor, Memory, and Storage Devices [patent_app_type] => utility [patent_app_number] => 17/854785 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13434 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -40 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854785 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854785
Doped BiSb (012) or undoped BiSb (001) topological insulator with GeNiFe buffer layer and/or interlayer for SOT based sensor, memory, and storage devices Jun 29, 2022 Issued
Array ( [id] => 19796083 [patent_doc_number] => 12237048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Memory device, memory system having the same, and method of operating the same [patent_app_type] => utility [patent_app_number] => 17/852593 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 9639 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17852593 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/852593
Memory device, memory system having the same, and method of operating the same Jun 28, 2022 Issued
Array ( [id] => 19654265 [patent_doc_number] => 12176065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Channel routing for simultaneous switching outputs [patent_app_type] => utility [patent_app_number] => 17/849197 [patent_app_country] => US [patent_app_date] => 2022-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4420 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17849197 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/849197
Channel routing for simultaneous switching outputs Jun 23, 2022 Issued
Array ( [id] => 19416541 [patent_doc_number] => 12082403 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-09-03 [patent_title] => One time programmable bitcell with select device in isolated well [patent_app_type] => utility [patent_app_number] => 17/849413 [patent_app_country] => US [patent_app_date] => 2022-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6435 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17849413 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/849413
One time programmable bitcell with select device in isolated well Jun 23, 2022 Issued
Array ( [id] => 18060058 [patent_doc_number] => 20220391144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => READ BROADCAST OPERATIONS ASSOCIATED WITH A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/846715 [patent_app_country] => US [patent_app_date] => 2022-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 44112 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17846715 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/846715
Read broadcast operations associated with a memory device Jun 21, 2022 Issued
Array ( [id] => 18865592 [patent_doc_number] => 20230420029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => SYSTEM FOR DETERMINING TARGET LOCKING TIME OF DELAY LOCKED LOOP OF MEMORY APPARATUS [patent_app_type] => utility [patent_app_number] => 17/846213 [patent_app_country] => US [patent_app_date] => 2022-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7696 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17846213 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/846213
System for determining target locking time of delay locked loop of memory apparatus Jun 21, 2022 Issued
Array ( [id] => 18394556 [patent_doc_number] => 20230162777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => METHOD FOR REFRESHING ROW HAMMER, CIRCUIT FOR REFRESHING ROW HAMMER AND SEMICONDUCTOR MEMORY [patent_app_type] => utility [patent_app_number] => 17/807478 [patent_app_country] => US [patent_app_date] => 2022-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11053 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17807478 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/807478
Method for refreshing row hammer, circuit for refreshing row hammer and semiconductor memory Jun 16, 2022 Issued
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