
Muna A. Techane
Examiner (ID: 6002, Phone: (571)272-7856 , Office: P/2827 )
| Most Active Art Unit | 2827 |
| Art Unit(s) | 2827 |
| Total Applications | 804 |
| Issued Applications | 695 |
| Pending Applications | 83 |
| Abandoned Applications | 41 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
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[patent_title] => One-time programmable (OTP) arrays with metal-semiconductor-metal (MSM) selectors for integrated circuitry
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