Search

Muna A. Techane

Examiner (ID: 10301, Phone: (571)272-7856 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
779
Issued Applications
676
Pending Applications
77
Abandoned Applications
41

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18155921 [patent_doc_number] => 11568910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 17/550338 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 63 [patent_no_of_words] => 40599 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17550338 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/550338
Memory system Dec 13, 2021 Issued
Array ( [id] => 18918996 [patent_doc_number] => 11881284 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-23 [patent_title] => Open translation unit management using an adaptive read threshold [patent_app_type] => utility [patent_app_number] => 17/546431 [patent_app_country] => US [patent_app_date] => 2021-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8447 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17546431 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/546431
Open translation unit management using an adaptive read threshold Dec 8, 2021 Issued
Array ( [id] => 18190426 [patent_doc_number] => 11581027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Memory sense amplifier trimming [patent_app_type] => utility [patent_app_number] => 17/543046 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6722 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17543046 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/543046
Memory sense amplifier trimming Dec 5, 2021 Issued
Array ( [id] => 18205230 [patent_doc_number] => 11587632 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-02-21 [patent_title] => Semiconductor device structure having fuse elements [patent_app_type] => utility [patent_app_number] => 17/542705 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9207 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17542705 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/542705
Semiconductor device structure having fuse elements Dec 5, 2021 Issued
Array ( [id] => 18967224 [patent_doc_number] => 11901002 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => RRAM filament spatial localization using a laser stimulation [patent_app_type] => utility [patent_app_number] => 17/539295 [patent_app_country] => US [patent_app_date] => 2021-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 9806 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17539295 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/539295
RRAM filament spatial localization using a laser stimulation Nov 30, 2021 Issued
Array ( [id] => 17764530 [patent_doc_number] => 20220238143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => TRIM/TEST INTERFACE FOR DEVICES WITH LOW PIN COUNT OR ANALOG OR NO-CONNECT PINS [patent_app_type] => utility [patent_app_number] => 17/537872 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8148 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17537872 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/537872
Trim/test interface for devices with low pin count or analog or no-connect pins Nov 29, 2021 Issued
Array ( [id] => 18408647 [patent_doc_number] => 20230170000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => Memory with Single-Ended Sensing Using Reset-Set Latch [patent_app_type] => utility [patent_app_number] => 17/456773 [patent_app_country] => US [patent_app_date] => 2021-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7293 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17456773 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/456773
Memory with single-ended sensing using reset-set latch Nov 28, 2021 Issued
Array ( [id] => 17676368 [patent_doc_number] => 20220189535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => MEMORY CONTROLLER AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/536803 [patent_app_country] => US [patent_app_date] => 2021-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4470 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17536803 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/536803
Memory controller and memory system Nov 28, 2021 Issued
Array ( [id] => 18935254 [patent_doc_number] => 11887692 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Electronic device, operation method of host, operation method of memory module, and operation method of memory device [patent_app_type] => utility [patent_app_number] => 17/535861 [patent_app_country] => US [patent_app_date] => 2021-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 19648 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17535861 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/535861
Electronic device, operation method of host, operation method of memory module, and operation method of memory device Nov 25, 2021 Issued
Array ( [id] => 17463468 [patent_doc_number] => 20220076774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => PROCESSING METHOD OF CHIP PROBING DATA AND COMPUTER-READABLE STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 17/455913 [patent_app_country] => US [patent_app_date] => 2021-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6379 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17455913 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/455913
Processing method of chip probing data and computer-readable storage medium Nov 19, 2021 Issued
Array ( [id] => 18431432 [patent_doc_number] => 11676659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Memory with expandable row width [patent_app_type] => utility [patent_app_number] => 17/530815 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7305 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530815 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/530815
Memory with expandable row width Nov 18, 2021 Issued
Array ( [id] => 18061473 [patent_doc_number] => 20220392559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => MEMORY SYSTEM INCLUDING A SUB-CONTROLLER AND OPERATING METHOD OF THE SUB-CONTROLLER [patent_app_type] => utility [patent_app_number] => 17/529970 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7936 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529970 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/529970
Memory system including a sub-controller and operating method of the sub-controller Nov 17, 2021 Issued
Array ( [id] => 17463858 [patent_doc_number] => 20220077164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => VARIABLE LOW RESISTANCE LINE NONVOLATILE MEMORY DEVICE AND METHOD FOR OPERATING SAME [patent_app_type] => utility [patent_app_number] => 17/527368 [patent_app_country] => US [patent_app_date] => 2021-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10688 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17527368 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/527368
VARIABLE LOW RESISTANCE LINE NONVOLATILE MEMORY DEVICE AND METHOD FOR OPERATING SAME Nov 15, 2021 Abandoned
Array ( [id] => 17963376 [patent_doc_number] => 20220343957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/526398 [patent_app_country] => US [patent_app_date] => 2021-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17526398 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/526398
Semiconductor memory device and memory system including the same Nov 14, 2021 Issued
Array ( [id] => 18181259 [patent_doc_number] => 20230041988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => SEMICONDUCTOR DEVICES FOR CONTROLLING REPAIR OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/525315 [patent_app_country] => US [patent_app_date] => 2021-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14045 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17525315 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/525315
Semiconductor devices for controlling repair operations Nov 11, 2021 Issued
Array ( [id] => 18248812 [patent_doc_number] => 11605408 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-03-14 [patent_title] => Merged command decoder for half-frequency circuits of a memory device [patent_app_type] => utility [patent_app_number] => 17/518153 [patent_app_country] => US [patent_app_date] => 2021-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6046 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17518153 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/518153
Merged command decoder for half-frequency circuits of a memory device Nov 2, 2021 Issued
Array ( [id] => 17447831 [patent_doc_number] => 20220068336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => MEMORY [patent_app_type] => utility [patent_app_number] => 17/517766 [patent_app_country] => US [patent_app_date] => 2021-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3868 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17517766 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/517766
Memory Nov 2, 2021 Issued
Array ( [id] => 18334996 [patent_doc_number] => 20230126944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => TECHNIQUES FOR INDICATING ROW ACTIVATION [patent_app_type] => utility [patent_app_number] => 17/511314 [patent_app_country] => US [patent_app_date] => 2021-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20211 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17511314 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/511314
Techniques for indicating row activation Oct 25, 2021 Issued
Array ( [id] => 19828591 [patent_doc_number] => 12249382 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Reading circuit for differential OTP memory [patent_app_type] => utility [patent_app_number] => 18/257946 [patent_app_country] => US [patent_app_date] => 2021-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 9922 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18257946 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/257946
Reading circuit for differential OTP memory Oct 20, 2021 Issued
Array ( [id] => 17431844 [patent_doc_number] => 20220059553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => MEMORY CELL AND METHOD FOR READING OUT DATA THEREFROM [patent_app_type] => utility [patent_app_number] => 17/451160 [patent_app_country] => US [patent_app_date] => 2021-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5494 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17451160 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/451160
Memory cell and method for reading out data therefrom Oct 17, 2021 Issued
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