Search

Muna A. Techane

Examiner (ID: 6002, Phone: (571)272-7856 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
804
Issued Applications
695
Pending Applications
83
Abandoned Applications
41

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17447831 [patent_doc_number] => 20220068336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => MEMORY [patent_app_type] => utility [patent_app_number] => 17/517766 [patent_app_country] => US [patent_app_date] => 2021-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3868 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17517766 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/517766
Memory Nov 2, 2021 Issued
Array ( [id] => 18248812 [patent_doc_number] => 11605408 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-03-14 [patent_title] => Merged command decoder for half-frequency circuits of a memory device [patent_app_type] => utility [patent_app_number] => 17/518153 [patent_app_country] => US [patent_app_date] => 2021-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6046 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17518153 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/518153
Merged command decoder for half-frequency circuits of a memory device Nov 2, 2021 Issued
Array ( [id] => 18334996 [patent_doc_number] => 20230126944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => TECHNIQUES FOR INDICATING ROW ACTIVATION [patent_app_type] => utility [patent_app_number] => 17/511314 [patent_app_country] => US [patent_app_date] => 2021-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20211 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17511314 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/511314
Techniques for indicating row activation Oct 25, 2021 Issued
Array ( [id] => 19828591 [patent_doc_number] => 12249382 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Reading circuit for differential OTP memory [patent_app_type] => utility [patent_app_number] => 18/257946 [patent_app_country] => US [patent_app_date] => 2021-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 9922 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18257946 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/257946
Reading circuit for differential OTP memory Oct 20, 2021 Issued
Array ( [id] => 17431844 [patent_doc_number] => 20220059553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => MEMORY CELL AND METHOD FOR READING OUT DATA THEREFROM [patent_app_type] => utility [patent_app_number] => 17/451160 [patent_app_country] => US [patent_app_date] => 2021-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5494 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17451160 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/451160
Memory cell and method for reading out data therefrom Oct 17, 2021 Issued
Array ( [id] => 18174952 [patent_doc_number] => 11574669 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Distribution-following access operations for a memory device [patent_app_type] => utility [patent_app_number] => 17/502451 [patent_app_country] => US [patent_app_date] => 2021-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 21580 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17502451 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/502451
Distribution-following access operations for a memory device Oct 14, 2021 Issued
Array ( [id] => 18890849 [patent_doc_number] => 11869626 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Internal and external data transfer for stacked memory dies [patent_app_type] => utility [patent_app_number] => 17/502792 [patent_app_country] => US [patent_app_date] => 2021-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8411 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17502792 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/502792
Internal and external data transfer for stacked memory dies Oct 14, 2021 Issued
Array ( [id] => 19596789 [patent_doc_number] => 12154642 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Built-in memory tests for aircraft processing systems [patent_app_type] => utility [patent_app_number] => 17/500053 [patent_app_country] => US [patent_app_date] => 2021-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3867 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17500053 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/500053
Built-in memory tests for aircraft processing systems Oct 12, 2021 Issued
Array ( [id] => 19670643 [patent_doc_number] => 12183410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Data storage apparatus comprising cell section operable as dosimeter and method of operating [patent_app_type] => utility [patent_app_number] => 18/248542 [patent_app_country] => US [patent_app_date] => 2021-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 10446 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18248542 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/248542
Data storage apparatus comprising cell section operable as dosimeter and method of operating Oct 12, 2021 Issued
Array ( [id] => 18105306 [patent_doc_number] => 11545200 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-03 [patent_title] => Data control circuit for increasing maximum and minimum tolerance values of skew between DQS signal and clock signal during write operation and associated memory device [patent_app_type] => utility [patent_app_number] => 17/498773 [patent_app_country] => US [patent_app_date] => 2021-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7095 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17498773 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/498773
Data control circuit for increasing maximum and minimum tolerance values of skew between DQS signal and clock signal during write operation and associated memory device Oct 11, 2021 Issued
Array ( [id] => 18688137 [patent_doc_number] => 11783880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Operating method of memory device for extending synchronization of data clock signal, and operating method of electronic device including the same [patent_app_type] => utility [patent_app_number] => 17/496003 [patent_app_country] => US [patent_app_date] => 2021-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 16482 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17496003 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/496003
Operating method of memory device for extending synchronization of data clock signal, and operating method of electronic device including the same Oct 6, 2021 Issued
Array ( [id] => 18312165 [patent_doc_number] => 20230116065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => RE-PROGRAMMABLE INTEGRATED CIRCUIT ARCHITECTURE AND METHOD OF MANUFACTURE [patent_app_type] => utility [patent_app_number] => 17/488008 [patent_app_country] => US [patent_app_date] => 2021-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3157 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17488008 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/488008
Re-programmable integrated circuit architecture and method of manufacture Sep 27, 2021 Issued
Array ( [id] => 17956152 [patent_doc_number] => 11482265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Write leveling [patent_app_type] => utility [patent_app_number] => 17/486481 [patent_app_country] => US [patent_app_date] => 2021-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 14062 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17486481 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/486481
Write leveling Sep 26, 2021 Issued
Array ( [id] => 17346855 [patent_doc_number] => 20220013186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => DETERMINE SIGNAL AND NOISE CHARACTERISTICS CENTERED AT AN OPTIMIZED READ VOLTAGE [patent_app_type] => utility [patent_app_number] => 17/485096 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485096 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/485096
Determine signal and noise characteristics centered at an optimized read voltage Sep 23, 2021 Issued
Array ( [id] => 18464188 [patent_doc_number] => 11688481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Semiconductor memory devices with diode-connected MOS [patent_app_type] => utility [patent_app_number] => 17/484730 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6224 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17484730 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/484730
Semiconductor memory devices with diode-connected MOS Sep 23, 2021 Issued
Array ( [id] => 19296162 [patent_doc_number] => 12035539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Magnetic memory and reading/writing method thereof [patent_app_type] => utility [patent_app_number] => 17/480357 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5680 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480357 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/480357
Magnetic memory and reading/writing method thereof Sep 20, 2021 Issued
Array ( [id] => 18387085 [patent_doc_number] => 11657874 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Semiconductor storage device [patent_app_type] => utility [patent_app_number] => 17/480858 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8915 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480858 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/480858
Semiconductor storage device Sep 20, 2021 Issued
Array ( [id] => 18827503 [patent_doc_number] => 11842792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Interface circuit, data transmission circuit, and memory [patent_app_type] => utility [patent_app_number] => 17/479184 [patent_app_country] => US [patent_app_date] => 2021-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8374 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17479184 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/479184
Interface circuit, data transmission circuit, and memory Sep 19, 2021 Issued
Array ( [id] => 17917164 [patent_doc_number] => 20220319560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => MEMORY CIRCUIT, METHOD AND DEVICE FOR CONTROLLING PRE-CHARGING OF MEMORY [patent_app_type] => utility [patent_app_number] => 17/470895 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11053 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470895 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/470895
Memory circuit, method and device for controlling pre-charging of memory Sep 8, 2021 Issued
Array ( [id] => 19031261 [patent_doc_number] => 11930636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Transistor antifuse, and related devices, systems, and methods [patent_app_type] => utility [patent_app_number] => 17/468523 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 9340 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468523 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/468523
Transistor antifuse, and related devices, systems, and methods Sep 6, 2021 Issued
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