Search

Muna A. Techane

Examiner (ID: 6002, Phone: (571)272-7856 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
804
Issued Applications
695
Pending Applications
83
Abandoned Applications
41

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18118988 [patent_doc_number] => 11550381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Non-volatile memory system or sub-system [patent_app_type] => utility [patent_app_number] => 17/468155 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11849 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468155 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/468155
Non-volatile memory system or sub-system Sep 6, 2021 Issued
Array ( [id] => 17978441 [patent_doc_number] => 11495313 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-08 [patent_title] => Fail-safe IC production testing [patent_app_type] => utility [patent_app_number] => 17/463631 [patent_app_country] => US [patent_app_date] => 2021-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5267 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463631 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/463631
Fail-safe IC production testing Aug 31, 2021 Issued
Array ( [id] => 18721252 [patent_doc_number] => 11798604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Memory architecture having ranks with variable data widths [patent_app_type] => utility [patent_app_number] => 17/464407 [patent_app_country] => US [patent_app_date] => 2021-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4853 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17464407 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/464407
Memory architecture having ranks with variable data widths Aug 31, 2021 Issued
Array ( [id] => 18105316 [patent_doc_number] => 11545210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Apparatuses, systems, and methods for fuse array based device identification [patent_app_type] => utility [patent_app_number] => 17/446569 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6661 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446569 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/446569
Apparatuses, systems, and methods for fuse array based device identification Aug 30, 2021 Issued
Array ( [id] => 18431449 [patent_doc_number] => 11676676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Merged bit lines for high density memory array [patent_app_type] => utility [patent_app_number] => 17/461898 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7106 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461898 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461898
Merged bit lines for high density memory array Aug 29, 2021 Issued
Array ( [id] => 17886130 [patent_doc_number] => 20220301607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => MEMORY SYSTEM AND DELAY CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 17/459536 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11713 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459536 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/459536
Memory system and delay control method Aug 26, 2021 Issued
Array ( [id] => 17645014 [patent_doc_number] => 20220172753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => MEMORY DEVICE, MEMORY SYSTEM, AND OPERATING METHOD OF MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/409064 [patent_app_country] => US [patent_app_date] => 2021-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17409064 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/409064
Memory device, memory system, and operating method of memory system Aug 22, 2021 Issued
Array ( [id] => 18219326 [patent_doc_number] => 11594272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Sensing a memory cell [patent_app_type] => utility [patent_app_number] => 17/409608 [patent_app_country] => US [patent_app_date] => 2021-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 16657 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17409608 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/409608
Sensing a memory cell Aug 22, 2021 Issued
Array ( [id] => 18998928 [patent_doc_number] => 11915782 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Semiconductor device and electronic device including the same [patent_app_type] => utility [patent_app_number] => 17/407585 [patent_app_country] => US [patent_app_date] => 2021-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9238 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17407585 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/407585
Semiconductor device and electronic device including the same Aug 19, 2021 Issued
Array ( [id] => 18357661 [patent_doc_number] => 11646067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Data storage device and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/407557 [patent_app_country] => US [patent_app_date] => 2021-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 7612 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17407557 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/407557
Data storage device and operating method thereof Aug 19, 2021 Issued
Array ( [id] => 18766752 [patent_doc_number] => 11817159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-14 [patent_title] => Circuit for detecting anti-fuse memory cell state and memory [patent_app_type] => utility [patent_app_number] => 17/445372 [patent_app_country] => US [patent_app_date] => 2021-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4601 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17445372 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/445372
Circuit for detecting anti-fuse memory cell state and memory Aug 17, 2021 Issued
Array ( [id] => 17978407 [patent_doc_number] => 11495279 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-08 [patent_title] => Managing write disturb for units of memory in a memory sub-system using a randomized refresh period [patent_app_type] => utility [patent_app_number] => 17/402984 [patent_app_country] => US [patent_app_date] => 2021-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8208 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17402984 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/402984
Managing write disturb for units of memory in a memory sub-system using a randomized refresh period Aug 15, 2021 Issued
Array ( [id] => 18578741 [patent_doc_number] => 11735280 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Memory device and operating method of the same [patent_app_type] => utility [patent_app_number] => 17/401907 [patent_app_country] => US [patent_app_date] => 2021-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11813 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17401907 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/401907
Memory device and operating method of the same Aug 12, 2021 Issued
Array ( [id] => 18782003 [patent_doc_number] => 11823768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Drive circuit and memory chip [patent_app_type] => utility [patent_app_number] => 17/401270 [patent_app_country] => US [patent_app_date] => 2021-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6600 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17401270 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/401270
Drive circuit and memory chip Aug 11, 2021 Issued
Array ( [id] => 18918993 [patent_doc_number] => 11881281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-23 [patent_title] => Dual reference voltage generator, equalizer circuit, and memory [patent_app_type] => utility [patent_app_number] => 17/398180 [patent_app_country] => US [patent_app_date] => 2021-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6265 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17398180 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/398180
Dual reference voltage generator, equalizer circuit, and memory Aug 9, 2021 Issued
Array ( [id] => 20507910 [patent_doc_number] => 12542192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => Stacked memory and manufacturing method therefor [patent_app_type] => utility [patent_app_number] => 18/681760 [patent_app_country] => US [patent_app_date] => 2021-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3689 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18681760 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/681760
Stacked memory and manufacturing method therefor Aug 5, 2021 Issued
Array ( [id] => 18669701 [patent_doc_number] => 11776611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Managing write disturb for units of a memory device using weighted write disturb counts [patent_app_type] => utility [patent_app_number] => 17/393013 [patent_app_country] => US [patent_app_date] => 2021-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 9415 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17393013 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/393013
Managing write disturb for units of a memory device using weighted write disturb counts Aug 2, 2021 Issued
Array ( [id] => 17878381 [patent_doc_number] => 11450402 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-20 [patent_title] => Sensing circuit and test device [patent_app_type] => utility [patent_app_number] => 17/392273 [patent_app_country] => US [patent_app_date] => 2021-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7950 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17392273 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/392273
Sensing circuit and test device Aug 2, 2021 Issued
Array ( [id] => 18219334 [patent_doc_number] => 11594280 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Content addressable memory device having electrically floating body transistor [patent_app_type] => utility [patent_app_number] => 17/390998 [patent_app_country] => US [patent_app_date] => 2021-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 103 [patent_figures_cnt] => 139 [patent_no_of_words] => 29436 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17390998 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/390998
Content addressable memory device having electrically floating body transistor Jul 31, 2021 Issued
Array ( [id] => 18890831 [patent_doc_number] => 11869608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Anti-fuse unit and anti-fuse array [patent_app_type] => utility [patent_app_number] => 17/384945 [patent_app_country] => US [patent_app_date] => 2021-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2657 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17384945 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/384945
Anti-fuse unit and anti-fuse array Jul 25, 2021 Issued
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