Muna A. Techane

Array ( [id] => 17978405 [patent_doc_number] => 11495277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Apparatus performing read operation [patent_app_type] => utility [patent_app_number] => 17/365636 [patent_app_country] => US [patent_app_date] => 2021-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10176 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17365636 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18080730 [patent_doc_number] => 20220406342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => Sense Amplifier Mapping and Control Scheme for Non-Volatile Memory [patent_app_type] => utility [patent_app_number] => 17/354613 [patent_app_country] => US [patent_app_date] => 2021-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17358 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17354613 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18190424 [patent_doc_number] => 11581025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => High resolution ZQ calibration method using hidden least significant bit (HLSB) [patent_app_type] => utility [patent_app_number] => 17/346853 [patent_app_country] => US [patent_app_date] => 2021-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12281 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17346853 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17862624 [patent_doc_number] => 11443785 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Memory device for generating data strobe signal based on pulse amplitude modulation, memory controller, and memory system including the same [patent_app_type] => utility [patent_app_number] => 17/344610 [patent_app_country] => US [patent_app_date] => 2021-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 8894 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17344610 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17745439 [patent_doc_number] => 11393518 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-07-19 [patent_title] => Memory cell arrangement and methods thereof [patent_app_type] => utility [patent_app_number] => 17/341884 [patent_app_country] => US [patent_app_date] => 2021-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 25167 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17341884 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17941476 [patent_doc_number] => 11475935 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-18 [patent_title] => Memory cell arrangement and methods thereof [patent_app_type] => utility [patent_app_number] => 17/341880 [patent_app_country] => US [patent_app_date] => 2021-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 23935 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17341880 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17833400 [patent_doc_number] => 20220270704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => TEST METHOD FOR SELF-REFRESH FREQUENCY OF MEMORY ARRAY AND MEMORY ARRAY TEST DEVICE [patent_app_type] => utility [patent_app_number] => 17/438431 [patent_app_country] => US [patent_app_date] => 2021-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4868 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17438431 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17115283 [patent_doc_number] => 20210295880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-23 [patent_title] => NON-VOLATILE MEMORY DEVICES AND SYSTEMS WITH VOLATILE MEMORY FEATURES AND METHODS FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/339846 [patent_app_country] => US [patent_app_date] => 2021-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3508 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17339846 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17447823 [patent_doc_number] => 20220068328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => Computing-In-Memory Architecture [patent_app_type] => utility [patent_app_number] => 17/337889 [patent_app_country] => US [patent_app_date] => 2021-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3805 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17337889 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17833352 [patent_doc_number] => 20220270656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => DIVIDING CIRCUIT SYSTEM AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THEREOF [patent_app_type] => utility [patent_app_number] => 17/331918 [patent_app_country] => US [patent_app_date] => 2021-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6297 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17331918 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18039701 [patent_doc_number] => 20220383918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => MEMORY ARRAY CIRCUITS INCLUDING WORD LINE CIRCUITS FOR IMPROVED WORD LINE SIGNAL TIMING AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 17/332629 [patent_app_country] => US [patent_app_date] => 2021-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9362 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17332629 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17085251 [patent_doc_number] => 20210280258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => METHODS OF ENHANCING SPEED OF READING DATA FROM MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/330290 [patent_app_country] => US [patent_app_date] => 2021-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5340 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17330290 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17395688 [patent_doc_number] => 11244709 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Write operation circuit, semiconductor memory, and write operation method [patent_app_type] => utility [patent_app_number] => 17/313003 [patent_app_country] => US [patent_app_date] => 2021-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 7437 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17313003 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17992991 [patent_doc_number] => 20220359028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => ADJUSTMENT TO TRIM SETTINGS BASED ON A USE OF A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/307798 [patent_app_country] => US [patent_app_date] => 2021-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8520 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17307798 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17025201 [patent_doc_number] => 20210249073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => ONE SELECTOR ONE RESISTOR RAM THRESHOLD VOLTAGE DRIFT AND OFFSET VOLTAGE COMPENSATION METHODS [patent_app_type] => utility [patent_app_number] => 17/245651 [patent_app_country] => US [patent_app_date] => 2021-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12890 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17245651 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17262356 [patent_doc_number] => 20210375341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => Phase-Aware DDR Command Dynamic Scheduling [patent_app_type] => utility [patent_app_number] => 17/246385 [patent_app_country] => US [patent_app_date] => 2021-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10095 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17246385 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17676349 [patent_doc_number] => 20220189516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => PIPE LATCH CIRCUIT, OPERATING METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/242639 [patent_app_country] => US [patent_app_date] => 2021-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6620 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17242639 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18669703 [patent_doc_number] => 11776613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => DRAM, memory controller and associated training method [patent_app_type] => utility [patent_app_number] => 17/238000 [patent_app_country] => US [patent_app_date] => 2021-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 6546 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17238000 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17010680 [patent_doc_number] => 20210241841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => SEMICONDUCTOR DEVICE HAVING A DIODE TYPE ELECTRICAL FUSE (E-FUSE) CELL ARRAY [patent_app_type] => utility [patent_app_number] => 17/237907 [patent_app_country] => US [patent_app_date] => 2021-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9531 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17237907 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17543867 [patent_doc_number] => 11308997 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-19 [patent_title] => Method and system for direct access to flash modules [patent_app_type] => utility [patent_app_number] => 17/228205 [patent_app_country] => US [patent_app_date] => 2021-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7880 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17228205 [rel_patent_id] =>[rel_patent_doc_number] =>)