Search

Muna A. Techane

Examiner (ID: 931, Phone: (571)272-7856 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
771
Issued Applications
673
Pending Applications
72
Abandoned Applications
41

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20488396 [patent_doc_number] => 20260024597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-22 [patent_title] => DUAL WORD LINE ALL-STRING PREPROGRAM FOR LATERAL DATA RETENTION IMPROVEMENT [patent_app_type] => utility [patent_app_number] => 18/776363 [patent_app_country] => US [patent_app_date] => 2024-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18776363 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/776363
DUAL WORD LINE ALL-STRING PREPROGRAM FOR LATERAL DATA RETENTION IMPROVEMENT Jul 17, 2024 Pending
Array ( [id] => 19531487 [patent_doc_number] => 20240355389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => RESISTIVE MEMORY WITH LOW VOLTAGE OPERATION [patent_app_type] => utility [patent_app_number] => 18/760971 [patent_app_country] => US [patent_app_date] => 2024-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5977 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18760971 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/760971
Resistive memory with low voltage operation Jun 30, 2024 Issued
Array ( [id] => 20448110 [patent_doc_number] => 20260004834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => Magnetic Memory Device and Method for Using the Same [patent_app_type] => utility [patent_app_number] => 18/761264 [patent_app_country] => US [patent_app_date] => 2024-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18761264 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/761264
Magnetic Memory Device and Method for Using the Same Jun 30, 2024 Pending
Array ( [id] => 20111296 [patent_doc_number] => 12362031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Indicating a status of a memory built-in self-test for multiple memory device ranks [patent_app_type] => utility [patent_app_number] => 18/756406 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 14498 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18756406 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/756406
Indicating a status of a memory built-in self-test for multiple memory device ranks Jun 26, 2024 Issued
Array ( [id] => 19712532 [patent_doc_number] => 20250022674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => DEVICES AND METHODS FOR PROGRAMMING A FUSE [patent_app_type] => utility [patent_app_number] => 18/751162 [patent_app_country] => US [patent_app_date] => 2024-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5480 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18751162 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/751162
Devices and methods for programming a fuse Jun 20, 2024 Issued
Array ( [id] => 19483744 [patent_doc_number] => 20240331786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => MEMORY DEVICE AND METHODS [patent_app_type] => utility [patent_app_number] => 18/741021 [patent_app_country] => US [patent_app_date] => 2024-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16162 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741021 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/741021
Memory device and methods Jun 11, 2024 Issued
Array ( [id] => 20396707 [patent_doc_number] => 20250372182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => ENHANCED DE-NOISING FOR RANDOM TELEGRAPH NOISE [patent_app_type] => utility [patent_app_number] => 18/733321 [patent_app_country] => US [patent_app_date] => 2024-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10756 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733321 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/733321
ENHANCED DE-NOISING FOR RANDOM TELEGRAPH NOISE Jun 3, 2024 Pending
Array ( [id] => 20222753 [patent_doc_number] => 20250285684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => SEQUENTIAL ERASE FOR TUNING THE PROGRAM STATE OF NON-VOLATILE MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/733750 [patent_app_country] => US [patent_app_date] => 2024-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733750 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/733750
SEQUENTIAL ERASE FOR TUNING THE PROGRAM STATE OF NON-VOLATILE MEMORY CELLS Jun 3, 2024 Pending
Array ( [id] => 20396686 [patent_doc_number] => 20250372161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => RETENTION MODE LOW LEAKAGE HIGH PERFORMANCE BIT LINE CLAMPING SCHEME BASED ON AN OUTPUT LATCH STATE [patent_app_type] => utility [patent_app_number] => 18/680945 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18680945 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/680945
RETENTION MODE LOW LEAKAGE HIGH PERFORMANCE BIT LINE CLAMPING SCHEME BASED ON AN OUTPUT LATCH STATE May 30, 2024 Pending
Array ( [id] => 19900058 [patent_doc_number] => 12277990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Memory device and method of operating the same [patent_app_type] => utility [patent_app_number] => 18/677095 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1182 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677095 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/677095
Memory device and method of operating the same May 28, 2024 Issued
Array ( [id] => 20396660 [patent_doc_number] => 20250372135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/676826 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9111 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18676826 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/676826
MEMORY DEVICE AND METHOD OF OPERATING THE SAME May 28, 2024 Pending
Array ( [id] => 19589421 [patent_doc_number] => 20240386978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/655437 [patent_app_country] => US [patent_app_date] => 2024-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6419 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18655437 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/655437
SEMICONDUCTOR INTEGRATED CIRCUIT May 5, 2024 Pending
Array ( [id] => 19574889 [patent_doc_number] => 20240379181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => APPARATUSES AND METHODS FOR READ DATA PRECONDITIONING USING A NEURAL NETWORK [patent_app_type] => utility [patent_app_number] => 18/650444 [patent_app_country] => US [patent_app_date] => 2024-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5216 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18650444 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/650444
APPARATUSES AND METHODS FOR READ DATA PRECONDITIONING USING A NEURAL NETWORK Apr 29, 2024 Pending
Array ( [id] => 20324342 [patent_doc_number] => 20250336430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => MANAGEMENT OF REFRESH OPERATIONS IN AN EMBEDDED DYNAMIC RANDOM ACCESS MEMORIES (DRAMS) HAVING CANARY CELLS [patent_app_type] => utility [patent_app_number] => 18/649586 [patent_app_country] => US [patent_app_date] => 2024-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18649586 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/649586
Management of refresh operations in an embedded dynamic random access memories (DRAMs) having canary cells Apr 28, 2024 Issued
Array ( [id] => 19406897 [patent_doc_number] => 20240290408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => MEMORY DEVICE AND OPERATING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 18/650058 [patent_app_country] => US [patent_app_date] => 2024-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11708 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18650058 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/650058
Memory device and operating method of the same Apr 28, 2024 Issued
Array ( [id] => 20530170 [patent_doc_number] => 12548611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Memory device using data strobe signal and method for compensating skew of data strobe signal thereof [patent_app_type] => utility [patent_app_number] => 18/647853 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7108 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18647853 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/647853
Memory device using data strobe signal and method for compensating skew of data strobe signal thereof Apr 25, 2024 Issued
Array ( [id] => 20053405 [patent_doc_number] => 20250191627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => DEVICE WITH IMPROVED DATA RECEIVING LOGIC USING MULTIPLE LATCHING AND METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/646670 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6334 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18646670 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/646670
DEVICE WITH IMPROVED DATA RECEIVING LOGIC USING MULTIPLE LATCHING AND METHOD THEREOF Apr 24, 2024 Pending
Array ( [id] => 19781300 [patent_doc_number] => 12230338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Semiconductor memory devices with diode-connected MOS [patent_app_type] => utility [patent_app_number] => 18/626971 [patent_app_country] => US [patent_app_date] => 2024-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18626971 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/626971
Semiconductor memory devices with diode-connected MOS Apr 3, 2024 Issued
Array ( [id] => 19812191 [patent_doc_number] => 12243599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Merged bit lines for high density memory array [patent_app_type] => utility [patent_app_number] => 18/627427 [patent_app_country] => US [patent_app_date] => 2024-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7152 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18627427 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/627427
Merged bit lines for high density memory array Apr 3, 2024 Issued
Array ( [id] => 20283379 [patent_doc_number] => 20250308621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => COLUMN REDUNDANCY DATA CIRCUITS AND METHODS FOR HIGHER TRANSMIT SPEED [patent_app_type] => utility [patent_app_number] => 18/623189 [patent_app_country] => US [patent_app_date] => 2024-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22567 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623189 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/623189
Column redundancy data circuits and methods for higher transmit speed Mar 31, 2024 Issued
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