Search

Muna A. Techane

Examiner (ID: 6002, Phone: (571)272-7856 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
804
Issued Applications
695
Pending Applications
83
Abandoned Applications
41

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18000727 [patent_doc_number] => 11501838 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Preread and read threshold voltage optimization [patent_app_type] => utility [patent_app_number] => 17/171486 [patent_app_country] => US [patent_app_date] => 2021-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10406 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17171486 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/171486
Preread and read threshold voltage optimization Feb 8, 2021 Issued
Array ( [id] => 17779868 [patent_doc_number] => 20220246218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => FLASH MEMORY AND FLASH MEMORY CELL THEREOF [patent_app_type] => utility [patent_app_number] => 17/166484 [patent_app_country] => US [patent_app_date] => 2021-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3535 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17166484 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/166484
Flash memory and flash memory cell thereof Feb 2, 2021 Issued
Array ( [id] => 18743121 [patent_doc_number] => 20230352109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => CURRENT-DRIVEN MAGNETIC DOMAIN-WALL LOGIC [patent_app_type] => utility [patent_app_number] => 17/909490 [patent_app_country] => US [patent_app_date] => 2021-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17909490 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/909490
CURRENT-DRIVEN MAGNETIC DOMAIN-WALL LOGIC Jan 25, 2021 Abandoned
Array ( [id] => 16850350 [patent_doc_number] => 20210151095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => REFRESH COMMAND CONTROL FOR HOST ASSIST OF ROW HAMMER MITIGATION [patent_app_type] => utility [patent_app_number] => 17/157826 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16245 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17157826 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/157826
Refresh command control for host assist of row hammer mitigation Jan 24, 2021 Issued
Array ( [id] => 17636716 [patent_doc_number] => 11347440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 17/148451 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 51 [patent_no_of_words] => 35416 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17148451 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/148451
Memory system Jan 12, 2021 Issued
Array ( [id] => 17636716 [patent_doc_number] => 11347440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 17/148451 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 51 [patent_no_of_words] => 35416 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17148451 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/148451
Memory system Jan 12, 2021 Issued
Array ( [id] => 17636716 [patent_doc_number] => 11347440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 17/148451 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 51 [patent_no_of_words] => 35416 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17148451 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/148451
Memory system Jan 12, 2021 Issued
Array ( [id] => 17636716 [patent_doc_number] => 11347440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 17/148451 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 51 [patent_no_of_words] => 35416 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17148451 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/148451
Memory system Jan 12, 2021 Issued
Array ( [id] => 18371651 [patent_doc_number] => 11651832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-16 [patent_title] => Memory device and test method thereof [patent_app_type] => utility [patent_app_number] => 17/146958 [patent_app_country] => US [patent_app_date] => 2021-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9721 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17146958 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/146958
Memory device and test method thereof Jan 11, 2021 Issued
Array ( [id] => 16951431 [patent_doc_number] => 20210210123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => PROCESSING-IN-MEMORY (PIM) SYSTEM AND OPERATING METHODS OF THE PIM SYSTEM [patent_app_type] => utility [patent_app_number] => 17/143886 [patent_app_country] => US [patent_app_date] => 2021-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31660 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17143886 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/143886
Processing-in-memory (PIM) system and operating methods of the PIM system Jan 6, 2021 Issued
Array ( [id] => 17373418 [patent_doc_number] => 20220028470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => MEMORY DEVICE, INTEGRATED CIRCUIT DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 17/143702 [patent_app_country] => US [patent_app_date] => 2021-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15915 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17143702 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/143702
Memory device, integrated circuit device and method Jan 6, 2021 Issued
Array ( [id] => 17069003 [patent_doc_number] => 20210271219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => SYSTEMS AND METHODS FOR MONITORING A POWER-GENERATION MODULE ASSEMBLY AFTER A POWER-GENERATION MODULE SHUTDOWN EVENT [patent_app_type] => utility [patent_app_number] => 17/133808 [patent_app_country] => US [patent_app_date] => 2020-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133808 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/133808
Systems and methods for monitoring a power-generation module assembly after a power-generation module shutdown event Dec 23, 2020 Issued
Array ( [id] => 17137442 [patent_doc_number] => 11139006 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-10-05 [patent_title] => Self-biased sense amplification circuit [patent_app_type] => utility [patent_app_number] => 17/131802 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4003 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17131802 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/131802
Self-biased sense amplification circuit Dec 22, 2020 Issued
Array ( [id] => 17691897 [patent_doc_number] => 20220199190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => METHODS TO LIMIT POWER DURING STRESS TEST AND OTHER LIMITED SUPPLIES ENVIRONMENT [patent_app_type] => utility [patent_app_number] => 17/125503 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9783 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17125503 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/125503
Methods to limit power during stress test and other limited supplies environment Dec 16, 2020 Issued
Array ( [id] => 17500422 [patent_doc_number] => 11289131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-29 [patent_title] => Dynamic control of multi-region fabric [patent_app_type] => utility [patent_app_number] => 17/113322 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5255 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17113322 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/113322
Dynamic control of multi-region fabric Dec 6, 2020 Issued
Array ( [id] => 17239370 [patent_doc_number] => 11183258 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-23 [patent_title] => Circuit and method for programming a one-time programmable memory [patent_app_type] => utility [patent_app_number] => 17/247282 [patent_app_country] => US [patent_app_date] => 2020-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7251 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17247282 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/247282
Circuit and method for programming a one-time programmable memory Dec 6, 2020 Issued
Array ( [id] => 16715791 [patent_doc_number] => 20210082938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => SINGLE POLY NON-VOLATILE MEMORY DEVICE, METHOD OF MANUFACTURING THE SAME AND SINGLE POLY NON-VOLATILE MEMORY DEVICE ARRAY [patent_app_type] => utility [patent_app_number] => 17/108444 [patent_app_country] => US [patent_app_date] => 2020-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8906 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17108444 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/108444
Single poly non-volatile memory device, method of manufacturing the same and single poly non-volatile memory device array Nov 30, 2020 Issued
Array ( [id] => 18122976 [patent_doc_number] => 20230008586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => METHOD FOR RESETTING AN ARRAY OF RESISTIVE MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/782423 [patent_app_country] => US [patent_app_date] => 2020-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5073 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17782423 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/782423
Method for resetting an array of resistive memory cells Nov 30, 2020 Issued
Array ( [id] => 17745434 [patent_doc_number] => 11393513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Timing of read and write operations to reduce interference, and related devices, systems, and methods [patent_app_type] => utility [patent_app_number] => 17/108850 [patent_app_country] => US [patent_app_date] => 2020-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8231 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17108850 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/108850
Timing of read and write operations to reduce interference, and related devices, systems, and methods Nov 30, 2020 Issued
Array ( [id] => 16715374 [patent_doc_number] => 20210082521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => LOW NOISE BIT LINE CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/107692 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8481 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107692 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/107692
Low noise bit line circuits Nov 29, 2020 Issued
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