Search

Muna A. Techane

Examiner (ID: 6002, Phone: (571)272-7856 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
804
Issued Applications
695
Pending Applications
83
Abandoned Applications
41

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17010644 [patent_doc_number] => 20210241805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => WRITE LEVELING [patent_app_type] => utility [patent_app_number] => 16/779866 [patent_app_country] => US [patent_app_date] => 2020-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14011 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16779866 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/779866
Write leveling Feb 2, 2020 Issued
Array ( [id] => 16271398 [patent_doc_number] => 20200272886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => ANALOG NEURAL MEMORY SYSTEM FOR DEEP LEARNING NEURAL NETWORK COMPRISING MULTIPLE VECTOR-BY-MATRIX MULTIPLICATION ARRAYS AND SHARED COMPONENTS [patent_app_type] => utility [patent_app_number] => 16/746837 [patent_app_country] => US [patent_app_date] => 2020-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12052 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16746837 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/746837
Analog neural memory system for deep learning neural network comprising multiple vector-by-matrix multiplication arrays and shared components Jan 17, 2020 Issued
Array ( [id] => 16873302 [patent_doc_number] => 20210166769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => METHODS OF ENHANCING SPEED OF READING DATA FROM MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/736754 [patent_app_country] => US [patent_app_date] => 2020-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5341 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16736754 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/736754
Methods of enhancing speed of reading data from memory device Jan 6, 2020 Issued
Array ( [id] => 17699961 [patent_doc_number] => 11373693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Method for adjusting reading speed of memory system, comparison circuit and memory system [patent_app_type] => utility [patent_app_number] => 17/254241 [patent_app_country] => US [patent_app_date] => 2019-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 9615 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17254241 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/254241
Method for adjusting reading speed of memory system, comparison circuit and memory system Dec 29, 2019 Issued
Array ( [id] => 17121940 [patent_doc_number] => 11133080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => Memory device and test operation method thereof [patent_app_type] => utility [patent_app_number] => 16/727282 [patent_app_country] => US [patent_app_date] => 2019-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 11339 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16727282 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/727282
Memory device and test operation method thereof Dec 25, 2019 Issued
Array ( [id] => 16973419 [patent_doc_number] => 11069398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Controller and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/727372 [patent_app_country] => US [patent_app_date] => 2019-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 7760 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16727372 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/727372
Controller and operating method thereof Dec 25, 2019 Issued
Array ( [id] => 17395716 [patent_doc_number] => 11244739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Counter-based read in memory device [patent_app_type] => utility [patent_app_number] => 16/771659 [patent_app_country] => US [patent_app_date] => 2019-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 21912 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16771659 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/771659
Counter-based read in memory device Dec 22, 2019 Issued
Array ( [id] => 17698871 [patent_doc_number] => 11372595 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Read broadcast operations associated with a memory device [patent_app_type] => utility [patent_app_number] => 17/414297 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 44085 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17414297 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/414297
Read broadcast operations associated with a memory device Dec 19, 2019 Issued
Array ( [id] => 17409425 [patent_doc_number] => 11250315 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => Electrochemical device of variable electrical conductance [patent_app_type] => utility [patent_app_number] => 16/666458 [patent_app_country] => US [patent_app_date] => 2019-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6868 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16666458 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/666458
Electrochemical device of variable electrical conductance Oct 28, 2019 Issued
Array ( [id] => 16795854 [patent_doc_number] => 20210125671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => INTEGRATED CIRCUIT AND COMPUTING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/667536 [patent_app_country] => US [patent_app_date] => 2019-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5320 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16667536 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/667536
Integrated circuit and computing method thereof Oct 28, 2019 Issued
Array ( [id] => 17145323 [patent_doc_number] => 20210313336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => VARIABLE LOW RESISTANCE LINE NONVOLATILE MEMORY DEVICE AND METHOD FOR OPERATING SAME [patent_app_type] => utility [patent_app_number] => 17/290630 [patent_app_country] => US [patent_app_date] => 2019-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17290630 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/290630
Variable low resistance line nonvolatile memory device and method for operating same Oct 23, 2019 Issued
Array ( [id] => 15791041 [patent_doc_number] => 10629249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Semiconductor device and semiconductor system [patent_app_type] => utility [patent_app_number] => 16/661800 [patent_app_country] => US [patent_app_date] => 2019-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7712 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16661800 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/661800
Semiconductor device and semiconductor system Oct 22, 2019 Issued
Array ( [id] => 17410010 [patent_doc_number] => 11250906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => Apparatus for compensating for radiation resistance of semiconductor memory, method therefor, and electronic circuit [patent_app_type] => utility [patent_app_number] => 17/057428 [patent_app_country] => US [patent_app_date] => 2019-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5437 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17057428 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/057428
Apparatus for compensating for radiation resistance of semiconductor memory, method therefor, and electronic circuit Oct 10, 2019 Issued
Array ( [id] => 15412499 [patent_doc_number] => 20200026572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-23 [patent_title] => APPARATUSES AND METHODS TO DETERMINE TIMING OF OPERATIONS [patent_app_type] => utility [patent_app_number] => 16/587554 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22833 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16587554 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/587554
Apparatuses and methods to determine timing of operations Sep 29, 2019 Issued
Array ( [id] => 15331025 [patent_doc_number] => 20200005842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => MEMORY DEVICE, OPERATING METHOD THEREOF, AND OPERATING METHOD OF MEMORY SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/567330 [patent_app_country] => US [patent_app_date] => 2019-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4081 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16567330 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/567330
Memory device, operating method thereof, and operating method of memory system including the same Sep 10, 2019 Issued
Array ( [id] => 16645326 [patent_doc_number] => 10923190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-16 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 16/566694 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 12508 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566694 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/566694
Memory device Sep 9, 2019 Issued
Array ( [id] => 17062926 [patent_doc_number] => 11107535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-31 [patent_title] => Memory device with adaptive noise and voltage suppression during read-while-write operations [patent_app_type] => utility [patent_app_number] => 16/566402 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6875 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566402 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/566402
Memory device with adaptive noise and voltage suppression during read-while-write operations Sep 9, 2019 Issued
Array ( [id] => 17018208 [patent_doc_number] => 11087853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Power-on over-erasure correction method and memory device utilizing same [patent_app_type] => utility [patent_app_number] => 16/565518 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5040 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16565518 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/565518
Power-on over-erasure correction method and memory device utilizing same Sep 9, 2019 Issued
Array ( [id] => 16987775 [patent_doc_number] => 11074954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-27 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 16/566396 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 16353 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566396 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/566396
Memory device Sep 9, 2019 Issued
Array ( [id] => 17310277 [patent_doc_number] => 11211404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-28 [patent_title] => Memory devices based on ferroelectric field effect transistors [patent_app_type] => utility [patent_app_number] => 16/565112 [patent_app_country] => US [patent_app_date] => 2019-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4628 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16565112 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/565112
Memory devices based on ferroelectric field effect transistors Sep 8, 2019 Issued
Menu