Muna A. Techane

Array ( [id] => 15759887 [patent_doc_number] => 10622070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => Ferroelectric memory device [patent_app_type] => utility [patent_app_number] => 16/142946 [patent_app_country] => US [patent_app_date] => 2018-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 21125 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16142946 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13847487 [patent_doc_number] => 20190027228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => CMOS Anti-Fuse Cell [patent_app_type] => utility [patent_app_number] => 16/143346 [patent_app_country] => US [patent_app_date] => 2018-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5669 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16143346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15656357 [patent_doc_number] => 20200090709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => APPARATUSES AND METHODS FOR PLATE COUPLED SENSE AMPLIFIERS [patent_app_type] => utility [patent_app_number] => 16/134732 [patent_app_country] => US [patent_app_date] => 2018-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11415 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16134732 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16536249 [patent_doc_number] => 10878862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Apparatuses and methods for DRAM wordline control with reverse temperature coefficient delay [patent_app_type] => utility [patent_app_number] => 16/133598 [patent_app_country] => US [patent_app_date] => 2018-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 10084 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16133598 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16034563 [patent_doc_number] => 10679708 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Pre-program read to counter wordline failures [patent_app_type] => utility [patent_app_number] => 16/133552 [patent_app_country] => US [patent_app_date] => 2018-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6189 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16133552 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13878203 [patent_doc_number] => 20190035442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => STACK ACCESS CONTROL FOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/133576 [patent_app_country] => US [patent_app_date] => 2018-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10082 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16133576 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14603083 [patent_doc_number] => 10354735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-16 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/116893 [patent_app_country] => US [patent_app_date] => 2018-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 63 [patent_no_of_words] => 20981 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16116893 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15060923 [patent_doc_number] => 10460773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Apparatuses and methods for converting a mask to an index [patent_app_type] => utility [patent_app_number] => 16/047949 [patent_app_country] => US [patent_app_date] => 2018-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 15354 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16047949 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16448118 [patent_doc_number] => 10840049 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Circuits, devices and methods for programming a fuse [patent_app_type] => utility [patent_app_number] => 16/035701 [patent_app_country] => US [patent_app_date] => 2018-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5358 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16035701 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13499299 [patent_doc_number] => 20180301192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => Content Addressable Memory Device Having Electrically Floating Body Transistor [patent_app_type] => utility [patent_app_number] => 16/013646 [patent_app_country] => US [patent_app_date] => 2018-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29275 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16013646 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13950309 [patent_doc_number] => 10210933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => System and method for adjusting EEPROM write cycle duration according to supply voltage variation [patent_app_type] => utility [patent_app_number] => 16/010268 [patent_app_country] => US [patent_app_date] => 2018-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3960 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16010268 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15045115 [patent_doc_number] => 20190333562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => SENSING A MEMORY CELL [patent_app_type] => utility [patent_app_number] => 15/962938 [patent_app_country] => US [patent_app_date] => 2018-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15962938 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15029917 [patent_doc_number] => 20190325963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => TERNARY MEMORY CELL AND TERNARY MEMORY CELL ARRANGEMENT [patent_app_type] => utility [patent_app_number] => 15/959688 [patent_app_country] => US [patent_app_date] => 2018-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14500 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15959688 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15029923 [patent_doc_number] => 20190325966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => NON-VOLATILE MEMORY DEVICES AND SYSTEMS WITH VOLATILE MEMORY FEATURES AND METHODS FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 15/959868 [patent_app_country] => US [patent_app_date] => 2018-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3471 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15959868 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16536279 [patent_doc_number] => 10878892 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Integrated circuit using discharging circuitries for bit lines [patent_app_type] => utility [patent_app_number] => 15/960482 [patent_app_country] => US [patent_app_date] => 2018-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8890 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15960482 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14475125 [patent_doc_number] => 20190189209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => NON-CONTACT ELECTRON BEAM PROBING TECHNIQUES AND RELATED STRUCTURES [patent_app_type] => utility [patent_app_number] => 15/918662 [patent_app_country] => US [patent_app_date] => 2018-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32772 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15918662 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16193911 [patent_doc_number] => 20200234760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-23 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/489912 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12569 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16489912 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12800023 [patent_doc_number] => 20180158510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => SRAM CELL FOR INTERLEAVED WORDLINE SCHEME [patent_app_type] => utility [patent_app_number] => 15/888517 [patent_app_country] => US [patent_app_date] => 2018-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15888517 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16201735 [patent_doc_number] => 10726910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Distributed sinking circuit control for memory device [patent_app_type] => utility [patent_app_number] => 15/874156 [patent_app_country] => US [patent_app_date] => 2018-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 10649 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15874156 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14587261 [patent_doc_number] => 20190221239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => Bitcell Wordline Strapping Circuitry [patent_app_type] => utility [patent_app_number] => 15/874444 [patent_app_country] => US [patent_app_date] => 2018-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5443 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15874444 [rel_patent_id] =>[rel_patent_doc_number] =>)