Search

Muna A. Techane

Examiner (ID: 6002, Phone: (571)272-7856 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
804
Issued Applications
695
Pending Applications
83
Abandoned Applications
41

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19589420 [patent_doc_number] => 20240386977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => HIGH-DENSITY & HIGH-VOLTAGE-TOLERABLE PURE CORE MEMORY CELL [patent_app_type] => utility [patent_app_number] => 18/787706 [patent_app_country] => US [patent_app_date] => 2024-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8193 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18787706 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/787706
HIGH-DENSITY & HIGH-VOLTAGE-TOLERABLE PURE CORE MEMORY CELL Jul 28, 2024 Pending
Array ( [id] => 19589411 [patent_doc_number] => 20240386968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => SYSTEM AND METHOD FOR RELIABLE SENSING OF MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/787791 [patent_app_country] => US [patent_app_date] => 2024-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8782 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18787791 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/787791
SYSTEM AND METHOD FOR RELIABLE SENSING OF MEMORY CELLS Jul 28, 2024 Pending
Array ( [id] => 20732965 [patent_doc_number] => 12640225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Memory device with a storage component [patent_app_type] => utility [patent_app_number] => 18/786291 [patent_app_country] => US [patent_app_date] => 2024-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5996 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18786291 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/786291
Memory device with a storage component Jul 25, 2024 Issued
Array ( [id] => 20732952 [patent_doc_number] => 12640212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Efficient empty page scan operations [patent_app_type] => utility [patent_app_number] => 18/785902 [patent_app_country] => US [patent_app_date] => 2024-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4938 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18785902 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/785902
Efficient empty page scan operations Jul 25, 2024 Issued
Array ( [id] => 20746630 [patent_doc_number] => 12646549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-02 [patent_title] => Non-linear polar material based multi-capacitor bit-cell with shared gain element with series transistor [patent_app_type] => utility [patent_app_number] => 18/781916 [patent_app_country] => US [patent_app_date] => 2024-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 56 [patent_no_of_words] => 34278 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18781916 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/781916
Non-linear polar material based multi-capacitor bit-cell with shared gain element with series transistor Jul 22, 2024 Issued
Array ( [id] => 20551406 [patent_doc_number] => 12562204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Non-linear polar material based multi-capacitor bit-cell with shared gain element with series transistor and individual access transistor [patent_app_type] => utility [patent_app_number] => 18/781878 [patent_app_country] => US [patent_app_date] => 2024-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 56 [patent_no_of_words] => 34283 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18781878 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/781878
Non-linear polar material based multi-capacitor bit-cell with shared gain element with series transistor and individual access transistor Jul 22, 2024 Issued
Array ( [id] => 20923803 [patent_doc_number] => 12718869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-25 [patent_title] => Apparatus including memory word line structure [patent_app_type] => utility [patent_app_number] => 18/780226 [patent_app_country] => US [patent_app_date] => 2024-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18780226 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/780226
Apparatus Including Memory Word Line Structure Jul 21, 2024 Pending
Array ( [id] => 20488396 [patent_doc_number] => 20260024597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-22 [patent_title] => DUAL WORD LINE ALL-STRING PREPROGRAM FOR LATERAL DATA RETENTION IMPROVEMENT [patent_app_type] => utility [patent_app_number] => 18/776363 [patent_app_country] => US [patent_app_date] => 2024-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18776363 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/776363
DUAL WORD LINE ALL-STRING PREPROGRAM FOR LATERAL DATA RETENTION IMPROVEMENT Jul 17, 2024 Pending
Array ( [id] => 19531487 [patent_doc_number] => 20240355389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => RESISTIVE MEMORY WITH LOW VOLTAGE OPERATION [patent_app_type] => utility [patent_app_number] => 18/760971 [patent_app_country] => US [patent_app_date] => 2024-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5977 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18760971 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/760971
Resistive memory with low voltage operation Jun 30, 2024 Issued
Array ( [id] => 20718074 [patent_doc_number] => 12633330 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-19 [patent_title] => Magnetic memory device and method for using the same [patent_app_type] => utility [patent_app_number] => 18/761264 [patent_app_country] => US [patent_app_date] => 2024-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 6762 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18761264 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/761264
Magnetic memory device and method for using the same Jun 30, 2024 Issued
Array ( [id] => 20111296 [patent_doc_number] => 12362031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Indicating a status of a memory built-in self-test for multiple memory device ranks [patent_app_type] => utility [patent_app_number] => 18/756406 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 14498 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18756406 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/756406
Indicating a status of a memory built-in self-test for multiple memory device ranks Jun 26, 2024 Issued
Array ( [id] => 19712532 [patent_doc_number] => 20250022674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => DEVICES AND METHODS FOR PROGRAMMING A FUSE [patent_app_type] => utility [patent_app_number] => 18/751162 [patent_app_country] => US [patent_app_date] => 2024-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5480 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18751162 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/751162
Devices and methods for programming a fuse Jun 20, 2024 Issued
Array ( [id] => 19483744 [patent_doc_number] => 20240331786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => MEMORY DEVICE AND METHODS [patent_app_type] => utility [patent_app_number] => 18/741021 [patent_app_country] => US [patent_app_date] => 2024-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16162 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741021 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/741021
Memory device and methods Jun 11, 2024 Issued
Array ( [id] => 20704057 [patent_doc_number] => 12626772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-12 [patent_title] => Enhanced de-noising for random telegraph noise [patent_app_type] => utility [patent_app_number] => 18/733321 [patent_app_country] => US [patent_app_date] => 2024-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10758 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733321 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/733321
Enhanced de-noising for random telegraph noise Jun 3, 2024 Issued
Array ( [id] => 20222753 [patent_doc_number] => 20250285684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => SEQUENTIAL ERASE FOR TUNING THE PROGRAM STATE OF NON-VOLATILE MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/733750 [patent_app_country] => US [patent_app_date] => 2024-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1257 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733750 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/733750
SEQUENTIAL ERASE FOR TUNING THE PROGRAM STATE OF NON-VOLATILE MEMORY CELLS Jun 3, 2024 Pending
Array ( [id] => 20396686 [patent_doc_number] => 20250372161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => RETENTION MODE LOW LEAKAGE HIGH PERFORMANCE BIT LINE CLAMPING SCHEME BASED ON AN OUTPUT LATCH STATE [patent_app_type] => utility [patent_app_number] => 18/680945 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18680945 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/680945
Retention mode low leakage high performance bit line clamping scheme based on an output latch state May 30, 2024 Issued
Array ( [id] => 19900058 [patent_doc_number] => 12277990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Memory device and method of operating the same [patent_app_type] => utility [patent_app_number] => 18/677095 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1182 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677095 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/677095
Memory device and method of operating the same May 28, 2024 Issued
Array ( [id] => 20396660 [patent_doc_number] => 20250372135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-04 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/676826 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9111 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18676826 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/676826
MEMORY DEVICE AND METHOD OF OPERATING THE SAME May 28, 2024 Pending
Array ( [id] => 19618932 [patent_doc_number] => 20240404612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => SEMICONDUCTOR DEVICE AND INKJET PRINTING ELEMENT SUBSTRATE [patent_app_type] => utility [patent_app_number] => 18/673427 [patent_app_country] => US [patent_app_date] => 2024-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8854 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18673427 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/673427
SEMICONDUCTOR DEVICE AND INKJET PRINTING ELEMENT SUBSTRATE May 23, 2024 Pending
Array ( [id] => 20915184 [patent_doc_number] => 12712038 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-18 [patent_title] => Semiconductor integrated circuit [patent_app_type] => utility [patent_app_number] => 18/655437 [patent_app_country] => US [patent_app_date] => 2024-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 1104 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18655437 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/655437
SEMICONDUCTOR INTEGRATED CIRCUIT May 5, 2024 Pending
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