Search

Muna A. Techane

Examiner (ID: 6002, Phone: (571)272-7856 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
804
Issued Applications
695
Pending Applications
83
Abandoned Applications
41

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16067243 [patent_doc_number] => 10692581 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Circuits for bleeding supply voltage from a device in a power down state [patent_app_type] => utility [patent_app_number] => 15/873812 [patent_app_country] => US [patent_app_date] => 2018-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4244 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15873812 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/873812
Circuits for bleeding supply voltage from a device in a power down state Jan 16, 2018 Issued
Array ( [id] => 15427385 [patent_doc_number] => 10546627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-28 [patent_title] => Semiconductor device and method of driving the same [patent_app_type] => utility [patent_app_number] => 15/873304 [patent_app_country] => US [patent_app_date] => 2018-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 8157 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15873304 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/873304
Semiconductor device and method of driving the same Jan 16, 2018 Issued
Array ( [id] => 12716134 [patent_doc_number] => 20180130544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/866094 [patent_app_country] => US [patent_app_date] => 2018-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14537 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15866094 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/866094
Semiconductor device and operating method thereof Jan 8, 2018 Issued
Array ( [id] => 15199829 [patent_doc_number] => 10497415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Dual gate memory devices [patent_app_type] => utility [patent_app_number] => 15/865144 [patent_app_country] => US [patent_app_date] => 2018-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 7593 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15865144 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/865144
Dual gate memory devices Jan 7, 2018 Issued
Array ( [id] => 14508947 [patent_doc_number] => 20190198128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => TEST SYSTEM AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 15/864374 [patent_app_country] => US [patent_app_date] => 2018-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7296 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15864374 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/864374
Test system and method of operating the same Jan 7, 2018 Issued
Array ( [id] => 14572985 [patent_doc_number] => 20190214100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => FAST DETECTION OF DEFECTIVE MEMORY BLOCK TO PREVENT NEIGHBOR PLANE DISTURB [patent_app_type] => utility [patent_app_number] => 15/863404 [patent_app_country] => US [patent_app_date] => 2018-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15863404 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/863404
Fast detection of defective memory block to prevent neighbor plane disturb Jan 4, 2018 Issued
Array ( [id] => 16845745 [patent_doc_number] => 11017839 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => DRAM, memory controller and associated training method [patent_app_type] => utility [patent_app_number] => 15/862884 [patent_app_country] => US [patent_app_date] => 2018-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 6529 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15862884 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/862884
DRAM, memory controller and associated training method Jan 4, 2018 Issued
Array ( [id] => 13613119 [patent_doc_number] => 20180358109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => MEMORY DEVICE, MEMORY SYSTEM, AND OPERATING METHOD OF MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/850152 [patent_app_country] => US [patent_app_date] => 2017-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7463 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15850152 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/850152
Memory device, memory system, and operating method of memory device Dec 20, 2017 Issued
Array ( [id] => 15580187 [patent_doc_number] => 10580485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => System and method for adjusting read levels in a storage device based on bias functions [patent_app_type] => utility [patent_app_number] => 15/849572 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7482 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15849572 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/849572
System and method for adjusting read levels in a storage device based on bias functions Dec 19, 2017 Issued
Array ( [id] => 14475181 [patent_doc_number] => 20190189237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => NON-CONTACT MEASUREMENT OF MEMORY CELL THRESHOLD VOLTAGE [patent_app_type] => utility [patent_app_number] => 15/849262 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15821 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15849262 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/849262
Non-contact measurement of memory cell threshold voltage Dec 19, 2017 Issued
Array ( [id] => 16536246 [patent_doc_number] => 10878859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Utilizing write stream attributes in storage write commands [patent_app_type] => utility [patent_app_number] => 15/849014 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6853 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15849014 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/849014
Utilizing write stream attributes in storage write commands Dec 19, 2017 Issued
Array ( [id] => 14475135 [patent_doc_number] => 20190189214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => SYSTEM AND METHOD FOR MINIMIZING FLOATING GATE TO FLOATING GATE COUPLING EFFECTS DURING PROGRAMMING IN FLASH MEMORY [patent_app_type] => utility [patent_app_number] => 15/849268 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3290 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15849268 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/849268
System and method for minimizing floating gate to floating gate coupling effects during programming in flash memory Dec 19, 2017 Issued
Array ( [id] => 12649746 [patent_doc_number] => 20180108413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => Method for Managing a Fail Row of the Memory Plane of a Non Volatile Memory and Corresponding Memory Device [patent_app_type] => utility [patent_app_number] => 15/842476 [patent_app_country] => US [patent_app_date] => 2017-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3878 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15842476 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/842476
Method for managing a fail row of the memory plane of a non volatile memory and corresponding memory device Dec 13, 2017 Issued
Array ( [id] => 14616571 [patent_doc_number] => 10360989 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Electronic device with a fuse-read trigger mechanism [patent_app_type] => utility [patent_app_number] => 15/830281 [patent_app_country] => US [patent_app_date] => 2017-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5247 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15830281 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/830281
Electronic device with a fuse-read trigger mechanism Dec 3, 2017 Issued
Array ( [id] => 14413363 [patent_doc_number] => 20190172525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-06 [patent_title] => MEMORY WITH EXPANDABLE ROW WIDTH [patent_app_type] => utility [patent_app_number] => 15/830176 [patent_app_country] => US [patent_app_date] => 2017-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15830176 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/830176
Memory with expandable row width Dec 3, 2017 Issued
Array ( [id] => 15014747 [patent_doc_number] => 10453529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => Resistive random access memory (RRAM) device, write verify method and reverse write verify method thereof [patent_app_type] => utility [patent_app_number] => 15/829987 [patent_app_country] => US [patent_app_date] => 2017-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3618 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15829987 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/829987
Resistive random access memory (RRAM) device, write verify method and reverse write verify method thereof Dec 3, 2017 Issued
Array ( [id] => 13875979 [patent_doc_number] => 20190034330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => MASS STORAGE DEVICE WITH DYNAMIC SINGLE LEVEL CELL (SLC) BUFFER SPECIFIC PROGRAM AND/OR ERASE SETTINGS [patent_app_type] => utility [patent_app_number] => 15/829764 [patent_app_country] => US [patent_app_date] => 2017-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4764 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15829764 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/829764
MASS STORAGE DEVICE WITH DYNAMIC SINGLE LEVEL CELL (SLC) BUFFER SPECIFIC PROGRAM AND/OR ERASE SETTINGS Nov 30, 2017 Abandoned
Array ( [id] => 13201099 [patent_doc_number] => 10115470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-30 [patent_title] => Circuit and method for biasing nonvolatile memory cells [patent_app_type] => utility [patent_app_number] => 15/804790 [patent_app_country] => US [patent_app_date] => 2017-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3209 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15804790 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/804790
Circuit and method for biasing nonvolatile memory cells Nov 5, 2017 Issued
Array ( [id] => 17121906 [patent_doc_number] => 11133046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => Data writing device for variable-resistance memory element and non-volatile flip-flop [patent_app_type] => utility [patent_app_number] => 16/339818 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11764 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16339818 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/339818
Data writing device for variable-resistance memory element and non-volatile flip-flop Oct 30, 2017 Issued
Array ( [id] => 15315011 [patent_doc_number] => 10522215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Reading circuit and method [patent_app_type] => utility [patent_app_number] => 15/797726 [patent_app_country] => US [patent_app_date] => 2017-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3642 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15797726 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/797726
Reading circuit and method Oct 29, 2017 Issued
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