Search

Muna A. Techane

Examiner (ID: 6002, Phone: (571)272-7856 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
804
Issued Applications
695
Pending Applications
83
Abandoned Applications
41

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19574889 [patent_doc_number] => 20240379181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => APPARATUSES AND METHODS FOR READ DATA PRECONDITIONING USING A NEURAL NETWORK [patent_app_type] => utility [patent_app_number] => 18/650444 [patent_app_country] => US [patent_app_date] => 2024-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5216 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18650444 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/650444
APPARATUSES AND METHODS FOR READ DATA PRECONDITIONING USING A NEURAL NETWORK Apr 29, 2024 Pending
Array ( [id] => 19406897 [patent_doc_number] => 20240290408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => MEMORY DEVICE AND OPERATING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 18/650058 [patent_app_country] => US [patent_app_date] => 2024-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11708 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18650058 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/650058
Memory device and operating method of the same Apr 28, 2024 Issued
Array ( [id] => 20324342 [patent_doc_number] => 20250336430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => MANAGEMENT OF REFRESH OPERATIONS IN AN EMBEDDED DYNAMIC RANDOM ACCESS MEMORIES (DRAMS) HAVING CANARY CELLS [patent_app_type] => utility [patent_app_number] => 18/649586 [patent_app_country] => US [patent_app_date] => 2024-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18649586 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/649586
Management of refresh operations in an embedded dynamic random access memories (DRAMs) having canary cells Apr 28, 2024 Issued
Array ( [id] => 20530170 [patent_doc_number] => 12548611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Memory device using data strobe signal and method for compensating skew of data strobe signal thereof [patent_app_type] => utility [patent_app_number] => 18/647853 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7108 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18647853 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/647853
Memory device using data strobe signal and method for compensating skew of data strobe signal thereof Apr 25, 2024 Issued
Array ( [id] => 20053405 [patent_doc_number] => 20250191627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => DEVICE WITH IMPROVED DATA RECEIVING LOGIC USING MULTIPLE LATCHING AND METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/646670 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6334 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18646670 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/646670
DEVICE WITH IMPROVED DATA RECEIVING LOGIC USING MULTIPLE LATCHING AND METHOD THEREOF Apr 24, 2024 Pending
Array ( [id] => 19812191 [patent_doc_number] => 12243599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Merged bit lines for high density memory array [patent_app_type] => utility [patent_app_number] => 18/627427 [patent_app_country] => US [patent_app_date] => 2024-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7152 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18627427 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/627427
Merged bit lines for high density memory array Apr 3, 2024 Issued
Array ( [id] => 19781300 [patent_doc_number] => 12230338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Semiconductor memory devices with diode-connected MOS [patent_app_type] => utility [patent_app_number] => 18/626971 [patent_app_country] => US [patent_app_date] => 2024-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18626971 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/626971
Semiconductor memory devices with diode-connected MOS Apr 3, 2024 Issued
Array ( [id] => 19483755 [patent_doc_number] => 20240331797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => MEMORY WITH ELECTRICALLY PROGRAMMABLE FUSES AND RELATED TESTER [patent_app_type] => utility [patent_app_number] => 18/623070 [patent_app_country] => US [patent_app_date] => 2024-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4153 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623070 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/623070
Memory with electrically programmable fuses and related tester Mar 31, 2024 Issued
Array ( [id] => 20283379 [patent_doc_number] => 20250308621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => COLUMN REDUNDANCY DATA CIRCUITS AND METHODS FOR HIGHER TRANSMIT SPEED [patent_app_type] => utility [patent_app_number] => 18/623189 [patent_app_country] => US [patent_app_date] => 2024-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22567 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623189 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/623189
Column redundancy data circuits and methods for higher transmit speed Mar 31, 2024 Issued
Array ( [id] => 20820102 [patent_doc_number] => 12675571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-07 [patent_title] => Guard rows to protect regions of memory [patent_app_type] => utility [patent_app_number] => 18/618861 [patent_app_country] => US [patent_app_date] => 2024-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 2533 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18618861 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/618861
Guard rows to protect regions of memory Mar 26, 2024 Issued
Array ( [id] => 20746621 [patent_doc_number] => 12646540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-02 [patent_title] => Memory device generating voltage responsive to temperature and method of operating the same [patent_app_type] => utility [patent_app_number] => 18/615790 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1081 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18615790 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/615790
Memory device generating voltage responsive to temperature and method of operating the same Mar 24, 2024 Issued
Array ( [id] => 20258813 [patent_doc_number] => 12431174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Fuse delay of a command in a memory package [patent_app_type] => utility [patent_app_number] => 18/615399 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1259 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18615399 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/615399
Fuse delay of a command in a memory package Mar 24, 2024 Issued
Array ( [id] => 20019345 [patent_doc_number] => 20250157567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => MEMORY DEVICE AND OPERATION METHOD THEREOF, MEMORY SYSTEM, AND COMPUTER SYSTEM [patent_app_type] => utility [patent_app_number] => 18/612859 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7573 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18612859 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/612859
Memory device and operation method thereof, memory system, and computer system Mar 20, 2024 Issued
Array ( [id] => 20718070 [patent_doc_number] => 12633325 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-19 [patent_title] => Semiconductor storage device and method of controlling the same [patent_app_type] => utility [patent_app_number] => 18/609522 [patent_app_country] => US [patent_app_date] => 2024-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 29 [patent_no_of_words] => 8806 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18609522 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/609522
Semiconductor storage device and method of controlling the same Mar 18, 2024 Issued
Array ( [id] => 19679059 [patent_doc_number] => 12190930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Threshold voltage-programmable field effect transistor-based memory cells and look-up table implemented using the memory cells [patent_app_type] => utility [patent_app_number] => 18/607725 [patent_app_country] => US [patent_app_date] => 2024-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 10896 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18607725 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/607725
Threshold voltage-programmable field effect transistor-based memory cells and look-up table implemented using the memory cells Mar 17, 2024 Issued
Array ( [id] => 20235537 [patent_doc_number] => 20250292856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => MEMORY LIFECYCLE STATE SENSORS [patent_app_type] => utility [patent_app_number] => 18/608355 [patent_app_country] => US [patent_app_date] => 2024-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18608355 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/608355
Memory lifecycle state sensors Mar 17, 2024 Issued
Array ( [id] => 20332569 [patent_doc_number] => 12462853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Apparatuses and methods including multilevel command and address signals [patent_app_type] => utility [patent_app_number] => 18/604339 [patent_app_country] => US [patent_app_date] => 2024-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4260 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604339 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/604339
Apparatuses and methods including multilevel command and address signals Mar 12, 2024 Issued
Array ( [id] => 19269067 [patent_doc_number] => 20240212771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => MEMORY READOUT CIRCUIT AND METHOD [patent_app_type] => utility [patent_app_number] => 18/601100 [patent_app_country] => US [patent_app_date] => 2024-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15361 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18601100 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/601100
Memory readout circuit and method Mar 10, 2024 Issued
Array ( [id] => 20222762 [patent_doc_number] => 20250285693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => EMBEDDED ELECTRONIC FUSES [patent_app_type] => utility [patent_app_number] => 18/596246 [patent_app_country] => US [patent_app_date] => 2024-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8455 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18596246 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/596246
Embedded electronic fuses Mar 4, 2024 Issued
Array ( [id] => 20416632 [patent_doc_number] => 12499921 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Divided clock control [patent_app_type] => utility [patent_app_number] => 18/590760 [patent_app_country] => US [patent_app_date] => 2024-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8670 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18590760 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/590760
Divided clock control Feb 27, 2024 Issued
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