Search

Muna A. Techane

Examiner (ID: 6002, Phone: (571)272-7856 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
804
Issued Applications
695
Pending Applications
83
Abandoned Applications
41

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20214985 [patent_doc_number] => 12411637 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Read broadcast operations associated with a memory device [patent_app_type] => utility [patent_app_number] => 18/589184 [patent_app_country] => US [patent_app_date] => 2024-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 38638 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18589184 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/589184
Read broadcast operations associated with a memory device Feb 26, 2024 Issued
Array ( [id] => 20636580 [patent_doc_number] => 12597461 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-07 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 18/583574 [patent_app_country] => US [patent_app_date] => 2024-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 3184 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18583574 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/583574
Memory device Feb 20, 2024 Issued
Array ( [id] => 20667366 [patent_doc_number] => 12609146 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-21 [patent_title] => Memory system performing hierarchical duty cycle adjuster training and duty cycle adjuster training method thereof [patent_app_type] => utility [patent_app_number] => 18/581187 [patent_app_country] => US [patent_app_date] => 2024-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8432 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581187 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/581187
Memory system performing hierarchical duty cycle adjuster training and duty cycle adjuster training method thereof Feb 18, 2024 Issued
Array ( [id] => 20732957 [patent_doc_number] => 12640217 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Apparatuses systems and methods for identification encoding for memory devices [patent_app_type] => utility [patent_app_number] => 18/444446 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1249 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18444446 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/444446
Apparatuses systems and methods for identification encoding for memory devices Feb 15, 2024 Issued
Array ( [id] => 19269075 [patent_doc_number] => 20240212779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => MEMORY SYSTEM INCLUDING A SUB-CONTROLLER AND OPERATING METHOD OF THE SUB-CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/438732 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7970 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18438732 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/438732
Memory system including a sub-controller and operating method of the sub-controller Feb 11, 2024 Issued
Array ( [id] => 19269075 [patent_doc_number] => 20240212779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => MEMORY SYSTEM INCLUDING A SUB-CONTROLLER AND OPERATING METHOD OF THE SUB-CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/438732 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7970 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18438732 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/438732
Memory system including a sub-controller and operating method of the sub-controller Feb 11, 2024 Issued
Array ( [id] => 19269075 [patent_doc_number] => 20240212779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => MEMORY SYSTEM INCLUDING A SUB-CONTROLLER AND OPERATING METHOD OF THE SUB-CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/438732 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7970 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18438732 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/438732
Memory system including a sub-controller and operating method of the sub-controller Feb 11, 2024 Issued
Array ( [id] => 19269075 [patent_doc_number] => 20240212779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => MEMORY SYSTEM INCLUDING A SUB-CONTROLLER AND OPERATING METHOD OF THE SUB-CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/438732 [patent_app_country] => US [patent_app_date] => 2024-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7970 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18438732 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/438732
Memory system including a sub-controller and operating method of the sub-controller Feb 11, 2024 Issued
Array ( [id] => 20793023 [patent_doc_number] => 12666957 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-23 [patent_title] => Anti-fuse cells with backside power rails [patent_app_type] => utility [patent_app_number] => 18/428920 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 35 [patent_no_of_words] => 11066 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428920 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/428920
Anti-fuse cells with backside power rails Jan 30, 2024 Issued
Array ( [id] => 19483720 [patent_doc_number] => 20240331762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => MEMORY DEVICE USING WORDLINE CALIBRATION FOR MATRIX VECTOR MULTIPLICATION [patent_app_type] => utility [patent_app_number] => 18/428992 [patent_app_country] => US [patent_app_date] => 2024-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18362 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428992 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/428992
MEMORY DEVICE USING WORDLINE CALIBRATION FOR MATRIX VECTOR MULTIPLICATION Jan 30, 2024 Pending
Array ( [id] => 20530168 [patent_doc_number] => 12548609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Feed-forward data toggling based delay circuit [patent_app_type] => utility [patent_app_number] => 18/425850 [patent_app_country] => US [patent_app_date] => 2024-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 4888 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18425850 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/425850
Feed-forward data toggling based delay circuit Jan 28, 2024 Issued
Array ( [id] => 19733579 [patent_doc_number] => 12211579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Memory sense amplifier trimming [patent_app_type] => utility [patent_app_number] => 18/424164 [patent_app_country] => US [patent_app_date] => 2024-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6764 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18424164 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/424164
Memory sense amplifier trimming Jan 25, 2024 Issued
Array ( [id] => 20276426 [patent_doc_number] => 12446215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => One-time programmable bitcell with a thermally enhanced rupture [patent_app_type] => utility [patent_app_number] => 18/413739 [patent_app_country] => US [patent_app_date] => 2024-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 3636 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18413739 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/413739
One-time programmable bitcell with a thermally enhanced rupture Jan 15, 2024 Issued
Array ( [id] => 20216196 [patent_doc_number] => 12412850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => One time programming memory cell and memory array for physically unclonable function technology and associated random code generating method [patent_app_type] => utility [patent_app_number] => 18/411064 [patent_app_country] => US [patent_app_date] => 2024-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 74 [patent_no_of_words] => 22263 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18411064 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/411064
One time programming memory cell and memory array for physically unclonable function technology and associated random code generating method Jan 11, 2024 Issued
Array ( [id] => 19145985 [patent_doc_number] => 20240145000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => MEMORY DEVICE AND METHOD FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/409760 [patent_app_country] => US [patent_app_date] => 2024-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5900 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18409760 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/409760
Memory device and method for operating the same Jan 9, 2024 Issued
Array ( [id] => 19670654 [patent_doc_number] => 12183421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Techniques for indicating row activation [patent_app_type] => utility [patent_app_number] => 18/408228 [patent_app_country] => US [patent_app_date] => 2024-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 20256 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18408228 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/408228
Techniques for indicating row activation Jan 8, 2024 Issued
Array ( [id] => 19654259 [patent_doc_number] => 12176059 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Internal and external data transfer for stacked memory dies [patent_app_type] => utility [patent_app_number] => 18/407062 [patent_app_country] => US [patent_app_date] => 2024-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8447 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18407062 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/407062
Internal and external data transfer for stacked memory dies Jan 7, 2024 Issued
Array ( [id] => 19145995 [patent_doc_number] => 20240145010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => PARTIAL BLOCK HANDLING IN A NON-VOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/404827 [patent_app_country] => US [patent_app_date] => 2024-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9385 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18404827 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/404827
Partial block handling in a non-volatile memory device Jan 3, 2024 Issued
Array ( [id] => 19148593 [patent_doc_number] => 20240147711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => MEMORY DEVICES, SEMICONDUCTOR DEVICES, AND METHODS OF OPERATIONS A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/404849 [patent_app_country] => US [patent_app_date] => 2024-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18527 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18404849 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/404849
Memory devices, semiconductor devices, and methods of operations a memory device Jan 3, 2024 Issued
Array ( [id] => 20381561 [patent_doc_number] => 20250364054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-27 [patent_title] => DEVICE AND METHOD FOR AUTOMATED DATA ERASURE IN NON-VOLATILE MEMORIES OF ELECTRONIC DEVICES [patent_app_type] => utility [patent_app_number] => 18/873856 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1371 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18873856 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/873856
DEVICE AND METHOD FOR AUTOMATED DATA ERASURE IN NON-VOLATILE MEMORIES OF ELECTRONIC DEVICES Dec 18, 2023 Pending
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