Search

Muna A. Techane

Examiner (ID: 6002, Phone: (571)272-7856 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
804
Issued Applications
695
Pending Applications
83
Abandoned Applications
41

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20898867 [patent_doc_number] => 12706135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-11 [patent_title] => Fast look neighbor ahead for data recovery [patent_app_type] => utility [patent_app_number] => 18/224839 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 31 [patent_no_of_words] => 8402 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 288 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18224839 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/224839
FAST LOOK NEIGHBOR AHEAD FOR DATA RECOVERY Jul 20, 2023 Pending
Array ( [id] => 19221196 [patent_doc_number] => 20240185900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => FAST REFERENCE VOLTAGE TRAINING FOR I/O INTERFACE [patent_app_type] => utility [patent_app_number] => 18/353294 [patent_app_country] => US [patent_app_date] => 2023-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23648 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18353294 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/353294
Fast reference voltage training for I/O interface Jul 16, 2023 Issued
Array ( [id] => 19348880 [patent_doc_number] => 20240257844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => MEMORY DEVICE INCLUDING A FILTERING CIRCUIT AND MEMORY SYSTEM INCLUDING THE MEMORY DEVICE AND FILTERING CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/349654 [patent_app_country] => US [patent_app_date] => 2023-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5708 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18349654 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/349654
Memory device including a filtering circuit and memory system including the memory device and filtering circuit Jul 9, 2023 Issued
Array ( [id] => 19918434 [patent_doc_number] => 12293807 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-06 [patent_title] => Offset calibration training method for adjusting data receiver offset and memory device therefor [patent_app_type] => utility [patent_app_number] => 18/347641 [patent_app_country] => US [patent_app_date] => 2023-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 3521 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18347641 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/347641
Offset calibration training method for adjusting data receiver offset and memory device therefor Jul 5, 2023 Issued
Array ( [id] => 18729109 [patent_doc_number] => 20230343404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-26 [patent_title] => MEMORY DEVICE AND OPERATING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 18/345530 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11675 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18345530 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/345530
Memory device and operating method of the same Jun 29, 2023 Issued
Array ( [id] => 19183576 [patent_doc_number] => 11990172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Refresh command control for host assist of row hammer mitigation [patent_app_type] => utility [patent_app_number] => 18/213231 [patent_app_country] => US [patent_app_date] => 2023-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 16292 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18213231 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/213231
Refresh command control for host assist of row hammer mitigation Jun 21, 2023 Issued
Array ( [id] => 19392482 [patent_doc_number] => 20240282352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => SEMICONDUCTOR SYSTEM FOR PERFORMING A DATA ALIGNMENT OPERATION [patent_app_type] => utility [patent_app_number] => 18/339101 [patent_app_country] => US [patent_app_date] => 2023-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18391 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18339101 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/339101
Semiconductor system for performing a data alignment operation Jun 20, 2023 Issued
Array ( [id] => 19646224 [patent_doc_number] => 20240420744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => SYSTEM FOR SHARING STATUS AMONG MULTIPLE DEVICES [patent_app_type] => utility [patent_app_number] => 18/209160 [patent_app_country] => US [patent_app_date] => 2023-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4923 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18209160 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/209160
System for sharing status among multiple devices Jun 12, 2023 Issued
Array ( [id] => 20507905 [patent_doc_number] => 12542187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => Apparatus and method to improve read window budget in a three dimensional NAND memory [patent_app_type] => utility [patent_app_number] => 18/206864 [patent_app_country] => US [patent_app_date] => 2023-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 1265 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18206864 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/206864
Apparatus and method to improve read window budget in a three dimensional NAND memory Jun 6, 2023 Issued
Array ( [id] => 19964659 [patent_doc_number] => 12334174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Electronic devices related to compensation of monitoring signals [patent_app_type] => utility [patent_app_number] => 18/330117 [patent_app_country] => US [patent_app_date] => 2023-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2143 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18330117 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/330117
Electronic devices related to compensation of monitoring signals Jun 5, 2023 Issued
Array ( [id] => 19093727 [patent_doc_number] => 11955191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Semiconductor memory devices with diode-connected MOS [patent_app_type] => utility [patent_app_number] => 18/328110 [patent_app_country] => US [patent_app_date] => 2023-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6245 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18328110 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/328110
Semiconductor memory devices with diode-connected MOS Jun 1, 2023 Issued
Array ( [id] => 19618931 [patent_doc_number] => 20240404611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => ONE-TIME-PROGRAMMABLE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/328091 [patent_app_country] => US [patent_app_date] => 2023-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5488 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18328091 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/328091
One-time-programmable memory devices Jun 1, 2023 Issued
Array ( [id] => 19358369 [patent_doc_number] => 12058852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Semiconductor device and method of operating the same [patent_app_type] => utility [patent_app_number] => 18/327876 [patent_app_country] => US [patent_app_date] => 2023-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 33 [patent_no_of_words] => 6055 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18327876 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/327876
Semiconductor device and method of operating the same May 31, 2023 Issued
Array ( [id] => 19145976 [patent_doc_number] => 20240144991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => MEMORY DEVICE ADJUSTING SKEW OF MULTI-PHASE CLOCK SIGNALS, MEMORY CONTROLLER CONTROLLING THE MEMORY DEVICE, AND OPERATING METHOD OF THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/326657 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12580 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18326657 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/326657
Memory device adjusting skew of multi-phase clock signals, memory controller controlling the memory device, and operating method of the memory device May 30, 2023 Issued
Array ( [id] => 19539244 [patent_doc_number] => 12131799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-29 [patent_title] => Trim/test interface for devices with low pin count or analog or no-connect pins [patent_app_type] => utility [patent_app_number] => 18/203806 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 8161 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18203806 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/203806
Trim/test interface for devices with low pin count or analog or no-connect pins May 30, 2023 Issued
Array ( [id] => 20354880 [patent_doc_number] => 20250351732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => MAGNETIC MEMORY ELEMENT, INFORMATION PROCESSING SYSTEM, AND METHOD FOR CONTROLLING MAGNETIC MEMORY ELEMENT [patent_app_type] => utility [patent_app_number] => 18/869003 [patent_app_country] => US [patent_app_date] => 2023-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3047 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18869003 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/869003
MAGNETIC MEMORY ELEMENT, INFORMATION PROCESSING SYSTEM, AND METHOD FOR CONTROLLING MAGNETIC MEMORY ELEMENT May 28, 2023 Pending
Array ( [id] => 19604415 [patent_doc_number] => 20240395295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => JITTER REDUCTION IN MIXED-SIGNAL PROCESSING CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/201611 [patent_app_country] => US [patent_app_date] => 2023-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5362 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18201611 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/201611
Jitter reduction in mixed-signal processing circuits May 23, 2023 Issued
Array ( [id] => 18820768 [patent_doc_number] => 20230395109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => MINIMUM MEMORY CLOCK ESTIMATION PROCEDURES [patent_app_type] => utility [patent_app_number] => 18/201089 [patent_app_country] => US [patent_app_date] => 2023-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10882 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18201089 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/201089
Minimum memory clock estimation procedures May 22, 2023 Issued
Array ( [id] => 19964669 [patent_doc_number] => 12334184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Bus inversion encoder module and bus inversion system including the same [patent_app_type] => utility [patent_app_number] => 18/318637 [patent_app_country] => US [patent_app_date] => 2023-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18318637 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/318637
Bus inversion encoder module and bus inversion system including the same May 15, 2023 Issued
Array ( [id] => 19093726 [patent_doc_number] => 11955190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Merged bit lines for high density memory array [patent_app_type] => utility [patent_app_number] => 18/317214 [patent_app_country] => US [patent_app_date] => 2023-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7135 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18317214 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/317214
Merged bit lines for high density memory array May 14, 2023 Issued
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