Search

Muna A. Techane

Examiner (ID: 12700, Phone: (571)272-7856 , Office: P/2827 )

Most Active Art Unit
2827
Art Unit(s)
2827
Total Applications
795
Issued Applications
692
Pending Applications
77
Abandoned Applications
41

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20507905 [patent_doc_number] => 12542187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => Apparatus and method to improve read window budget in a three dimensional NAND memory [patent_app_type] => utility [patent_app_number] => 18/206864 [patent_app_country] => US [patent_app_date] => 2023-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 1265 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18206864 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/206864
Apparatus and method to improve read window budget in a three dimensional NAND memory Jun 6, 2023 Issued
Array ( [id] => 19964659 [patent_doc_number] => 12334174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Electronic devices related to compensation of monitoring signals [patent_app_type] => utility [patent_app_number] => 18/330117 [patent_app_country] => US [patent_app_date] => 2023-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2143 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18330117 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/330117
Electronic devices related to compensation of monitoring signals Jun 5, 2023 Issued
Array ( [id] => 19618931 [patent_doc_number] => 20240404611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => ONE-TIME-PROGRAMMABLE MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/328091 [patent_app_country] => US [patent_app_date] => 2023-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5488 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18328091 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/328091
One-time-programmable memory devices Jun 1, 2023 Issued
Array ( [id] => 19093727 [patent_doc_number] => 11955191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Semiconductor memory devices with diode-connected MOS [patent_app_type] => utility [patent_app_number] => 18/328110 [patent_app_country] => US [patent_app_date] => 2023-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6245 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18328110 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/328110
Semiconductor memory devices with diode-connected MOS Jun 1, 2023 Issued
Array ( [id] => 19358369 [patent_doc_number] => 12058852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Semiconductor device and method of operating the same [patent_app_type] => utility [patent_app_number] => 18/327876 [patent_app_country] => US [patent_app_date] => 2023-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 33 [patent_no_of_words] => 6055 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18327876 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/327876
Semiconductor device and method of operating the same May 31, 2023 Issued
Array ( [id] => 19145976 [patent_doc_number] => 20240144991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => MEMORY DEVICE ADJUSTING SKEW OF MULTI-PHASE CLOCK SIGNALS, MEMORY CONTROLLER CONTROLLING THE MEMORY DEVICE, AND OPERATING METHOD OF THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/326657 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12580 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18326657 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/326657
Memory device adjusting skew of multi-phase clock signals, memory controller controlling the memory device, and operating method of the memory device May 30, 2023 Issued
Array ( [id] => 19539244 [patent_doc_number] => 12131799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-29 [patent_title] => Trim/test interface for devices with low pin count or analog or no-connect pins [patent_app_type] => utility [patent_app_number] => 18/203806 [patent_app_country] => US [patent_app_date] => 2023-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 8161 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18203806 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/203806
Trim/test interface for devices with low pin count or analog or no-connect pins May 30, 2023 Issued
Array ( [id] => 20354880 [patent_doc_number] => 20250351732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => MAGNETIC MEMORY ELEMENT, INFORMATION PROCESSING SYSTEM, AND METHOD FOR CONTROLLING MAGNETIC MEMORY ELEMENT [patent_app_type] => utility [patent_app_number] => 18/869003 [patent_app_country] => US [patent_app_date] => 2023-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3047 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18869003 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/869003
MAGNETIC MEMORY ELEMENT, INFORMATION PROCESSING SYSTEM, AND METHOD FOR CONTROLLING MAGNETIC MEMORY ELEMENT May 28, 2023 Pending
Array ( [id] => 19604415 [patent_doc_number] => 20240395295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => JITTER REDUCTION IN MIXED-SIGNAL PROCESSING CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/201611 [patent_app_country] => US [patent_app_date] => 2023-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5362 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18201611 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/201611
Jitter reduction in mixed-signal processing circuits May 23, 2023 Issued
Array ( [id] => 18820768 [patent_doc_number] => 20230395109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => MINIMUM MEMORY CLOCK ESTIMATION PROCEDURES [patent_app_type] => utility [patent_app_number] => 18/201089 [patent_app_country] => US [patent_app_date] => 2023-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10882 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18201089 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/201089
Minimum memory clock estimation procedures May 22, 2023 Issued
Array ( [id] => 19964669 [patent_doc_number] => 12334184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Bus inversion encoder module and bus inversion system including the same [patent_app_type] => utility [patent_app_number] => 18/318637 [patent_app_country] => US [patent_app_date] => 2023-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18318637 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/318637
Bus inversion encoder module and bus inversion system including the same May 15, 2023 Issued
Array ( [id] => 19093726 [patent_doc_number] => 11955190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Merged bit lines for high density memory array [patent_app_type] => utility [patent_app_number] => 18/317214 [patent_app_country] => US [patent_app_date] => 2023-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7135 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18317214 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/317214
Merged bit lines for high density memory array May 14, 2023 Issued
Array ( [id] => 18661009 [patent_doc_number] => 20230307022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/143967 [patent_app_country] => US [patent_app_date] => 2023-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18143967 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/143967
Semiconductor memory device and memory system including the same May 4, 2023 Issued
Array ( [id] => 19559624 [patent_doc_number] => 20240371416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => REDUCED CIRCUIT AREA MEMORY DEVICE WITH A HALF-WORD MEMORY ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/143560 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8792 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18143560 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/143560
Reduced circuit area memory device with a half-word memory architecture May 3, 2023 Issued
Array ( [id] => 18820834 [patent_doc_number] => 20230395175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => LOOPBACK DATAPATH FOR CLOCK QUALITY DETECTION [patent_app_type] => utility [patent_app_number] => 18/312280 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7334 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312280 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/312280
Loopback datapath for clock quality detection May 3, 2023 Issued
Array ( [id] => 19704725 [patent_doc_number] => 12198771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => Fuse link programming cell, programming circuit, control circuit, and array [patent_app_type] => utility [patent_app_number] => 18/141946 [patent_app_country] => US [patent_app_date] => 2023-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6058 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18141946 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/141946
Fuse link programming cell, programming circuit, control circuit, and array Apr 30, 2023 Issued
Array ( [id] => 18555044 [patent_doc_number] => 20230253060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => RE-PROGRAMMABLE INTEGRATED CIRCUIT ARCHITECTURE AND METHOD OF MANUFACTURE [patent_app_type] => utility [patent_app_number] => 18/134239 [patent_app_country] => US [patent_app_date] => 2023-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3174 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18134239 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/134239
RE-PROGRAMMABLE INTEGRATED CIRCUIT ARCHITECTURE AND METHOD OF MANUFACTURE Apr 12, 2023 Abandoned
Array ( [id] => 18555029 [patent_doc_number] => 20230253045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/299505 [patent_app_country] => US [patent_app_date] => 2023-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8942 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18299505 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/299505
Semiconductor storage device Apr 11, 2023 Issued
Array ( [id] => 20332595 [patent_doc_number] => 12462879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Memory device and operating method of the memory device [patent_app_type] => utility [patent_app_number] => 18/296789 [patent_app_country] => US [patent_app_date] => 2023-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 4865 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18296789 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/296789
Memory device and operating method of the memory device Apr 5, 2023 Issued
Array ( [id] => 20434897 [patent_doc_number] => 12505882 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-23 [patent_title] => Apparatus and method for programming and verifying data in a nonvolatile memory device [patent_app_type] => utility [patent_app_number] => 18/295726 [patent_app_country] => US [patent_app_date] => 2023-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11113 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18295726 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/295726
Apparatus and method for programming and verifying data in a nonvolatile memory device Apr 3, 2023 Issued
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