Muna A. Techane

Array ( [id] => 18661009 [patent_doc_number] => 20230307022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/143967 [patent_app_country] => US [patent_app_date] => 2023-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18143967 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18820834 [patent_doc_number] => 20230395175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => LOOPBACK DATAPATH FOR CLOCK QUALITY DETECTION [patent_app_type] => utility [patent_app_number] => 18/312280 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7334 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18312280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19559624 [patent_doc_number] => 20240371416 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => REDUCED CIRCUIT AREA MEMORY DEVICE WITH A HALF-WORD MEMORY ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 18/143560 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8792 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18143560 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19704725 [patent_doc_number] => 12198771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => Fuse link programming cell, programming circuit, control circuit, and array [patent_app_type] => utility [patent_app_number] => 18/141946 [patent_app_country] => US [patent_app_date] => 2023-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6058 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18141946 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18555044 [patent_doc_number] => 20230253060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => RE-PROGRAMMABLE INTEGRATED CIRCUIT ARCHITECTURE AND METHOD OF MANUFACTURE [patent_app_type] => utility [patent_app_number] => 18/134239 [patent_app_country] => US [patent_app_date] => 2023-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3174 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18134239 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18555029 [patent_doc_number] => 20230253045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/299505 [patent_app_country] => US [patent_app_date] => 2023-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8942 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18299505 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20332595 [patent_doc_number] => 12462879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Memory device and operating method of the memory device [patent_app_type] => utility [patent_app_number] => 18/296789 [patent_app_country] => US [patent_app_date] => 2023-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 4865 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18296789 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20434897 [patent_doc_number] => 12505882 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-23 [patent_title] => Apparatus and method for programming and verifying data in a nonvolatile memory device [patent_app_type] => utility [patent_app_number] => 18/295726 [patent_app_country] => US [patent_app_date] => 2023-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11113 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18295726 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19900049 [patent_doc_number] => 12277981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Anti-fuse cell structure, anti-fuse array, operation method for anti-fuse array, and memory [patent_app_type] => utility [patent_app_number] => 18/295839 [patent_app_country] => US [patent_app_date] => 2023-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2413 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18295839 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18532991 [patent_doc_number] => 20230238066 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => NON-VOLATILE MEMORY DEVICE, PROGRAMMING METHOD THEREOF, AND STORAGE DEVICE HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 18/128596 [patent_app_country] => US [patent_app_date] => 2023-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10410 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18128596 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18532996 [patent_doc_number] => 20230238071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => MEMORY READOUT CIRCUIT AND METHOD [patent_app_type] => utility [patent_app_number] => 18/190796 [patent_app_country] => US [patent_app_date] => 2023-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15343 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18190796 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18827501 [patent_doc_number] => 11842790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Page buffer circuit and memory device including the same [patent_app_type] => utility [patent_app_number] => 18/125260 [patent_app_country] => US [patent_app_date] => 2023-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 19981 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18125260 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18615548 [patent_doc_number] => 20230282285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => METHOD FOR PROGRAMMING MEMORY DEVICE, MEMORY DEVICE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/188992 [patent_app_country] => US [patent_app_date] => 2023-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18867 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18188992 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19943430 [patent_doc_number] => 12315566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Information processing device and memory system [patent_app_type] => utility [patent_app_number] => 18/184368 [patent_app_country] => US [patent_app_date] => 2023-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 1835 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18184368 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20455770 [patent_doc_number] => 12518830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 18/177779 [patent_app_country] => US [patent_app_date] => 2023-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 47 [patent_no_of_words] => 27219 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 338 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18177779 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18615564 [patent_doc_number] => 20230282301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => COUNTER-BASED READ IN MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/112307 [patent_app_country] => US [patent_app_date] => 2023-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21990 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18112307 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19392491 [patent_doc_number] => 20240282361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/111676 [patent_app_country] => US [patent_app_date] => 2023-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18111676 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19016096 [patent_doc_number] => 11923036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Memory sense amplifier trimming [patent_app_type] => utility [patent_app_number] => 18/168226 [patent_app_country] => US [patent_app_date] => 2023-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6733 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18168226 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18439675 [patent_doc_number] => 20230186970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => DECODING DRIVE CIRCUIT AND METHOD THEREFOR, WORD LINE DECODING CIRCUIT AND SEMICONDUCTOR MEMORY [patent_app_type] => utility [patent_app_number] => 18/166378 [patent_app_country] => US [patent_app_date] => 2023-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10537 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18166378 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19906333 [patent_doc_number] => 12283345 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Pulse generator, error check and scrub (ECS) circuit and memory [patent_app_type] => utility [patent_app_number] => 18/166034 [patent_app_country] => US [patent_app_date] => 2023-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 2456 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18166034 [rel_patent_id] =>[rel_patent_doc_number] =>)