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Mushfique Siddique

Examiner (ID: 1672, Phone: (571)270-0424 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
886
Issued Applications
722
Pending Applications
91
Abandoned Applications
88

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19828597 [patent_doc_number] => 12249388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Memory system and nonvolatile memory for improving reliability of stored data and shortening operation time [patent_app_type] => utility [patent_app_number] => 17/887985 [patent_app_country] => US [patent_app_date] => 2022-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 6847 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17887985 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/887985
Memory system and nonvolatile memory for improving reliability of stored data and shortening operation time Aug 14, 2022 Issued
Array ( [id] => 19046464 [patent_doc_number] => 11935583 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Integrated assemblies [patent_app_type] => utility [patent_app_number] => 17/887226 [patent_app_country] => US [patent_app_date] => 2022-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5806 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17887226 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/887226
Integrated assemblies Aug 11, 2022 Issued
Array ( [id] => 18488138 [patent_doc_number] => 20230215486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => MEMORY DEVICE AND OPERATING SYSTEM [patent_app_type] => utility [patent_app_number] => 17/884053 [patent_app_country] => US [patent_app_date] => 2022-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5956 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884053 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/884053
Memory device and memory system with a self-refresh function Aug 8, 2022 Issued
Array ( [id] => 18974952 [patent_doc_number] => 20240055044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => SYSTEMS AND METHODS FOR CONTROLLING COMMON MODE LEVEL FOR SENSE AMPLIFIER CIRCUITRY [patent_app_type] => utility [patent_app_number] => 17/884261 [patent_app_country] => US [patent_app_date] => 2022-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7259 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884261 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/884261
Systems and methods for controlling common mode level for sense amplifier circuitry Aug 8, 2022 Issued
Array ( [id] => 18585722 [patent_doc_number] => 20230267986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => TWO-STAGE VOLTAGE CALIBRATION UPON POWER-UP OF MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/883392 [patent_app_country] => US [patent_app_date] => 2022-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8040 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17883392 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/883392
Two-stage voltage calibration upon power-up of memory device Aug 7, 2022 Issued
Array ( [id] => 18008196 [patent_doc_number] => 20220366963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => FLASH MEMORY STORAGE APPARATUS AND A BIASING METHOD THEREOF, WHICH CAN REDUCE A GATE INDUCED DRAIN LEAKAGE (GIDL) AND IMPROVE RELIABILITY OF MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/874296 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2836 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874296 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/874296
FLASH MEMORY STORAGE APPARATUS AND A BIASING METHOD THEREOF, WHICH CAN REDUCE A GATE INDUCED DRAIN LEAKAGE (GIDL) AND IMPROVE RELIABILITY OF MEMORY CELLS Jul 26, 2022 Abandoned
Array ( [id] => 18630682 [patent_doc_number] => 20230289577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => NEURAL NETWORK SYSTEM, HIGH DENSITY EMBEDDED-ARTIFICIAL SYNAPTIC ELEMENT AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/813598 [patent_app_country] => US [patent_app_date] => 2022-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6233 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813598 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/813598
NEURAL NETWORK SYSTEM, HIGH DENSITY EMBEDDED-ARTIFICIAL SYNAPTIC ELEMENT AND OPERATING METHOD THEREOF Jul 18, 2022 Pending
Array ( [id] => 20243930 [patent_doc_number] => 12424260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Triggering a refresh for non-volatile memory [patent_app_type] => utility [patent_app_number] => 17/868074 [patent_app_country] => US [patent_app_date] => 2022-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 14822 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17868074 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/868074
Triggering a refresh for non-volatile memory Jul 18, 2022 Issued
Array ( [id] => 19679110 [patent_doc_number] => 12190981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Memory array having error checking and correction circuit [patent_app_type] => utility [patent_app_number] => 17/866558 [patent_app_country] => US [patent_app_date] => 2022-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5621 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17866558 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/866558
Memory array having error checking and correction circuit Jul 17, 2022 Issued
Array ( [id] => 17963383 [patent_doc_number] => 20220343964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => MEMORY SYSTEM CAPABLE OF COMPENSATING FOR KICKBACK NOISE [patent_app_type] => utility [patent_app_number] => 17/864237 [patent_app_country] => US [patent_app_date] => 2022-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14286 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17864237 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/864237
Memory system capable of compensating for kickback noise Jul 12, 2022 Issued
Array ( [id] => 18652835 [patent_doc_number] => 20230298675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => METHOD AND APPARATUS WITH FLASH MEMORY CONTROL [patent_app_type] => utility [patent_app_number] => 17/863556 [patent_app_country] => US [patent_app_date] => 2022-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7704 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17863556 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/863556
Method and apparatus with flash memory control Jul 12, 2022 Issued
Array ( [id] => 19427921 [patent_doc_number] => 12087349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Storage device and method of discharging an operating voltage [patent_app_type] => utility [patent_app_number] => 17/862472 [patent_app_country] => US [patent_app_date] => 2022-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 26 [patent_no_of_words] => 9806 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17862472 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/862472
Storage device and method of discharging an operating voltage Jul 11, 2022 Issued
Array ( [id] => 18555042 [patent_doc_number] => 20230253058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => MEMORY DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/862697 [patent_app_country] => US [patent_app_date] => 2022-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14959 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17862697 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/862697
Memory device and operating method for performing pre-program operation on over-erasure cells Jul 11, 2022 Issued
Array ( [id] => 18905755 [patent_doc_number] => 20240021240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => MEMORY DEVICES WITH IMPROVED BIT LINE LOADING [patent_app_type] => utility [patent_app_number] => 17/863092 [patent_app_country] => US [patent_app_date] => 2022-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8779 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17863092 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/863092
Memory devices with improved bit line loading Jul 11, 2022 Issued
Array ( [id] => 17963390 [patent_doc_number] => 20220343971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => SEMICONDUCTOR MEMORY DEVICE INCLUDING WORD LINE AND BIT LINE [patent_app_type] => utility [patent_app_number] => 17/862081 [patent_app_country] => US [patent_app_date] => 2022-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17862081 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/862081
Semiconductor memory device including word line and bit line Jul 10, 2022 Issued
Array ( [id] => 18446860 [patent_doc_number] => 11682435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-20 [patent_title] => Apparatuses and methods for detecting illegal commands and command sequences [patent_app_type] => utility [patent_app_number] => 17/811153 [patent_app_country] => US [patent_app_date] => 2022-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8015 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17811153 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/811153
Apparatuses and methods for detecting illegal commands and command sequences Jul 6, 2022 Issued
Array ( [id] => 18455877 [patent_doc_number] => 20230197158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => NONVOLATILE MEMORY DEVICES AND STORAGE DEVICES [patent_app_type] => utility [patent_app_number] => 17/810777 [patent_app_country] => US [patent_app_date] => 2022-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17243 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17810777 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/810777
Nonvolatile memory devices for reducing degradation due to difference of threshold voltage distributions between outer cells and inner cells Jul 4, 2022 Issued
Array ( [id] => 18631498 [patent_doc_number] => 20230290400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => EFFICIENT AND LOW POWER REFERENCE VOLTAGE MIXING [patent_app_type] => utility [patent_app_number] => 17/855094 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17855094 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/855094
Efficient and low power reference voltage mixing Jun 29, 2022 Issued
Array ( [id] => 19414505 [patent_doc_number] => 12080337 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Local amplifying circuit, data readout method and memory [patent_app_type] => utility [patent_app_number] => 17/854153 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 5312 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 380 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854153 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854153
Local amplifying circuit, data readout method and memory Jun 29, 2022 Issued
Array ( [id] => 19654225 [patent_doc_number] => 12176025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) [patent_app_type] => utility [patent_app_number] => 17/844955 [patent_app_country] => US [patent_app_date] => 2022-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 8833 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17844955 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/844955
Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) Jun 20, 2022 Issued
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