Search

Mushfique Siddique

Examiner (ID: 16359, Phone: (571)270-0424 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
838
Issued Applications
687
Pending Applications
93
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19679075 [patent_doc_number] => 12190946 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-01-07 [patent_title] => Read disturb mitigation for non-linear polar material based multi-capacitor bit-cell [patent_app_type] => utility [patent_app_number] => 17/805664 [patent_app_country] => US [patent_app_date] => 2022-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 32 [patent_no_of_words] => 27183 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17805664 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/805664
Read disturb mitigation for non-linear polar material based multi-capacitor bit-cell Jun 5, 2022 Issued
Array ( [id] => 19294326 [patent_doc_number] => 12033687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Computer memory systems employing localized generation of global bit line (GBL) clock signal to reduce clock signal read path divergence for improved signal tracking, and related methods [patent_app_type] => utility [patent_app_number] => 17/831129 [patent_app_country] => US [patent_app_date] => 2022-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11399 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17831129 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/831129
Computer memory systems employing localized generation of global bit line (GBL) clock signal to reduce clock signal read path divergence for improved signal tracking, and related methods Jun 1, 2022 Issued
Array ( [id] => 19356723 [patent_doc_number] => 12057178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Cell voltage drop compensation circuit [patent_app_type] => utility [patent_app_number] => 17/831266 [patent_app_country] => US [patent_app_date] => 2022-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4418 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17831266 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/831266
Cell voltage drop compensation circuit Jun 1, 2022 Issued
Array ( [id] => 19495734 [patent_doc_number] => 12114473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Three-port SRAM cell and layout method [patent_app_type] => utility [patent_app_number] => 17/828123 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12549 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17828123 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/828123
Three-port SRAM cell and layout method May 30, 2022 Issued
Array ( [id] => 17854905 [patent_doc_number] => 20220284948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => OPTIMIZED COLUMN READ ENABLED MEMORY [patent_app_type] => utility [patent_app_number] => 17/824808 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8038 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824808 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/824808
OPTIMIZED COLUMN READ ENABLED MEMORY May 24, 2022 Pending
Array ( [id] => 17854900 [patent_doc_number] => 20220284943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => SEMICONDUCTOR MEMORY DEVICE CAPABLE OF OPERATING AT HIGH SPEED, LOW POWER ENVIRONMENT BY OPTIMIZING LATENCY OF READ COMMAND AND WRITE COMMAND DEPENDING ON VARIOUS OPERATION MODES [patent_app_type] => utility [patent_app_number] => 17/824470 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14142 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824470 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/824470
Semiconductor memory device capable of operating at high speed, low power environment by optimizing latency of read command and write command depending on various operation modes May 24, 2022 Issued
Array ( [id] => 18812246 [patent_doc_number] => 20230386583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => ADAPTIVE POROGRAMMING DELAY SCHEME IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 17/752590 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17007 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17752590 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/752590
Adaptive programming delay scheme in a memory sub-system May 23, 2022 Issued
Array ( [id] => 18848510 [patent_doc_number] => 20230410914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => PROGRAMMING DELAY SCHEME FOR IN A MEMORY SUB-SYSTEM BASED ON MEMORY RELIABILITY [patent_app_type] => utility [patent_app_number] => 17/752579 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17752579 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/752579
Programming delay scheme for a memory sub-system based on memory reliability May 23, 2022 Issued
Array ( [id] => 19328590 [patent_doc_number] => 12046279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Multi-pass programming operation sequence in a memory device [patent_app_type] => utility [patent_app_number] => 17/751179 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 13753 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17751179 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/751179
Multi-pass programming operation sequence in a memory device May 22, 2022 Issued
Array ( [id] => 18789047 [patent_doc_number] => 20230377657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => PUMP SKIP FOR FAST SINGLE-LEVEL CELL NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 17/750938 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18271 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17750938 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/750938
Pump skip for fast single-level cell non-volatile memory May 22, 2022 Issued
Array ( [id] => 18789025 [patent_doc_number] => 20230377633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => THREE DIMENSION MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/751445 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4082 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17751445 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/751445
Three dimension memory device capable of improving sensing accuracy in high-speed data sensing operation May 22, 2022 Issued
Array ( [id] => 19610782 [patent_doc_number] => 12159662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Semiconductor device including write transistor and read transistor disposed on a plane substantially parallel to substrate [patent_app_type] => utility [patent_app_number] => 17/749131 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 10319 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17749131 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/749131
Semiconductor device including write transistor and read transistor disposed on a plane substantially parallel to substrate May 18, 2022 Issued
Array ( [id] => 18431424 [patent_doc_number] => 11676651 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Arithmetic devices conducting auto-load operation [patent_app_type] => utility [patent_app_number] => 17/747595 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 15683 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747595 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/747595
Arithmetic devices conducting auto-load operation May 17, 2022 Issued
Array ( [id] => 19093733 [patent_doc_number] => 11955197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Memory device and method for shifting memory values [patent_app_type] => utility [patent_app_number] => 17/746096 [patent_app_country] => US [patent_app_date] => 2022-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6559 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17746096 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/746096
Memory device and method for shifting memory values May 16, 2022 Issued
Array ( [id] => 18007450 [patent_doc_number] => 20220366216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => METHOD AND NON-TRANSITORY COMPUTER READABLE MEDIUM FOR COMPUTE-IN-MEMORY MACRO ARRANGEMENT, AND ELECTRONIC DEVICE APPLYING THE SAME [patent_app_type] => utility [patent_app_number] => 17/743476 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3419 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17743476 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/743476
METHOD AND NON-TRANSITORY COMPUTER READABLE MEDIUM FOR COMPUTE-IN-MEMORY MACRO ARRANGEMENT, AND ELECTRONIC DEVICE APPLYING THE SAME May 12, 2022 Pending
Array ( [id] => 17840488 [patent_doc_number] => 20220277794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => VOLTAGE SUPPLY CIRCUIT, MEMORY CELL ARRANGEMENT, AND METHOD FOR OPERATING A MEMORY CELL ARRANGEMENT [patent_app_type] => utility [patent_app_number] => 17/744473 [patent_app_country] => US [patent_app_date] => 2022-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23935 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17744473 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/744473
Voltage supply circuit, memory cell arrangement, and method for operating a memory cell arrangement May 12, 2022 Issued
Array ( [id] => 17833366 [patent_doc_number] => 20220270670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR IDENTIFYING VICTIM ROWS IN A MEMORY DEVICE WHICH CANNOT BE SIMULTANEOUSLY REFRESHED [patent_app_type] => utility [patent_app_number] => 17/662733 [patent_app_country] => US [patent_app_date] => 2022-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9325 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17662733 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/662733
Refresh modes for performing various refresh operation types May 9, 2022 Issued
Array ( [id] => 18164354 [patent_doc_number] => 20230030949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => SYNAPTIC DEVICE, RESERVOIR COMPUTING DEVICE INCLUDING THE SYNAPTIC DEVICE, AND RESERVOIR COMPUTING METHOD USING THE COMPUTING DEVICE [patent_app_type] => utility [patent_app_number] => 17/737369 [patent_app_country] => US [patent_app_date] => 2022-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5751 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17737369 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/737369
SYNAPTIC DEVICE, RESERVOIR COMPUTING DEVICE INCLUDING THE SYNAPTIC DEVICE, AND RESERVOIR COMPUTING METHOD USING THE COMPUTING DEVICE May 4, 2022 Pending
Array ( [id] => 19260677 [patent_doc_number] => 12020742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Compensating for concentrated activation of memory cells in a semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/734508 [patent_app_country] => US [patent_app_date] => 2022-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13960 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17734508 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/734508
Compensating for concentrated activation of memory cells in a semiconductor memory device May 1, 2022 Issued
Array ( [id] => 18743124 [patent_doc_number] => 20230352112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR PER ROW ERROR SCRUB INFORMATION REGISTERS [patent_app_type] => utility [patent_app_number] => 17/730396 [patent_app_country] => US [patent_app_date] => 2022-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8450 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17730396 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/730396
APPARATUSES, SYSTEMS, AND METHODS FOR PER ROW ERROR SCRUB INFORMATION REGISTERS Apr 26, 2022 Pending
Menu