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Mushfique Siddique

Examiner (ID: 1672, Phone: (571)270-0424 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
886
Issued Applications
722
Pending Applications
91
Abandoned Applications
88

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18488129 [patent_doc_number] => 20230215477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => MEMORY CONTROLLER AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/845259 [patent_app_country] => US [patent_app_date] => 2022-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6966 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17845259 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/845259
Memory controller performing training to improve communication and method of operating the same Jun 20, 2022 Issued
Array ( [id] => 20080569 [patent_doc_number] => 12354644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) [patent_app_type] => utility [patent_app_number] => 17/844434 [patent_app_country] => US [patent_app_date] => 2022-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 1209 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17844434 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/844434
Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM) Jun 19, 2022 Issued
Array ( [id] => 18661022 [patent_doc_number] => 20230307035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => METHOD AND APPARATUS FOR DETERMINING SENSE BOUNDARY OF SENSE AMPLIFIER, MEDIUM, AND DEVICE [patent_app_type] => utility [patent_app_number] => 17/807760 [patent_app_country] => US [patent_app_date] => 2022-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9961 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17807760 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/807760
Method and apparatus for determining sense boundary of sense amplifier, medium, and device Jun 19, 2022 Issued
Array ( [id] => 18271309 [patent_doc_number] => 20230092551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/806630 [patent_app_country] => US [patent_app_date] => 2022-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20054 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806630 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/806630
NAND flash programming and method of applying read pulse before end of program Jun 12, 2022 Issued
Array ( [id] => 18514375 [patent_doc_number] => 20230230630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-20 [patent_title] => READOUT CIRCUIT ARCHITECTURE AND SENSE AMPLIFICATION CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/836296 [patent_app_country] => US [patent_app_date] => 2022-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9923 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17836296 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/836296
Readout circuit layout and sense amplification circuit Jun 8, 2022 Issued
Array ( [id] => 19328624 [patent_doc_number] => 12046313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => OTP device with read module and biasing circuitry to detect and measure accurate breakdown states of anti-fuse memory cells [patent_app_type] => utility [patent_app_number] => 17/835917 [patent_app_country] => US [patent_app_date] => 2022-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5416 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 355 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17835917 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/835917
OTP device with read module and biasing circuitry to detect and measure accurate breakdown states of anti-fuse memory cells Jun 7, 2022 Issued
Array ( [id] => 20215969 [patent_doc_number] => 12412623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Precharge circuitry for use with bitlines [patent_app_type] => utility [patent_app_number] => 17/835912 [patent_app_country] => US [patent_app_date] => 2022-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1182 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17835912 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/835912
Precharge circuitry for use with bitlines Jun 7, 2022 Issued
Array ( [id] => 20691815 [patent_doc_number] => 12621986 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-05 [patent_title] => Memory device with peripheral circuitry which extends under a back end memory array [patent_app_type] => utility [patent_app_number] => 17/834679 [patent_app_country] => US [patent_app_date] => 2022-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11240 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 383 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17834679 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/834679
Memory device with peripheral circuitry which extends under a back end memory array Jun 6, 2022 Issued
Array ( [id] => 19679075 [patent_doc_number] => 12190946 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-01-07 [patent_title] => Read disturb mitigation for non-linear polar material based multi-capacitor bit-cell [patent_app_type] => utility [patent_app_number] => 17/805664 [patent_app_country] => US [patent_app_date] => 2022-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 32 [patent_no_of_words] => 27183 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17805664 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/805664
Read disturb mitigation for non-linear polar material based multi-capacitor bit-cell Jun 5, 2022 Issued
Array ( [id] => 19356723 [patent_doc_number] => 12057178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Cell voltage drop compensation circuit [patent_app_type] => utility [patent_app_number] => 17/831266 [patent_app_country] => US [patent_app_date] => 2022-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4418 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17831266 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/831266
Cell voltage drop compensation circuit Jun 1, 2022 Issued
Array ( [id] => 19294326 [patent_doc_number] => 12033687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Computer memory systems employing localized generation of global bit line (GBL) clock signal to reduce clock signal read path divergence for improved signal tracking, and related methods [patent_app_type] => utility [patent_app_number] => 17/831129 [patent_app_country] => US [patent_app_date] => 2022-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11399 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17831129 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/831129
Computer memory systems employing localized generation of global bit line (GBL) clock signal to reduce clock signal read path divergence for improved signal tracking, and related methods Jun 1, 2022 Issued
Array ( [id] => 19495734 [patent_doc_number] => 12114473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Three-port SRAM cell and layout method [patent_app_type] => utility [patent_app_number] => 17/828123 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12549 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17828123 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/828123
Three-port SRAM cell and layout method May 30, 2022 Issued
Array ( [id] => 17854900 [patent_doc_number] => 20220284943 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => SEMICONDUCTOR MEMORY DEVICE CAPABLE OF OPERATING AT HIGH SPEED, LOW POWER ENVIRONMENT BY OPTIMIZING LATENCY OF READ COMMAND AND WRITE COMMAND DEPENDING ON VARIOUS OPERATION MODES [patent_app_type] => utility [patent_app_number] => 17/824470 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14142 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824470 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/824470
Semiconductor memory device capable of operating at high speed, low power environment by optimizing latency of read command and write command depending on various operation modes May 24, 2022 Issued
Array ( [id] => 17854905 [patent_doc_number] => 20220284948 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => OPTIMIZED COLUMN READ ENABLED MEMORY [patent_app_type] => utility [patent_app_number] => 17/824808 [patent_app_country] => US [patent_app_date] => 2022-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8038 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824808 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/824808
Techniques to map and access column read enabled memory May 24, 2022 Issued
Array ( [id] => 18848510 [patent_doc_number] => 20230410914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => PROGRAMMING DELAY SCHEME FOR IN A MEMORY SUB-SYSTEM BASED ON MEMORY RELIABILITY [patent_app_type] => utility [patent_app_number] => 17/752579 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17752579 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/752579
Programming delay scheme for a memory sub-system based on memory reliability May 23, 2022 Issued
Array ( [id] => 18812246 [patent_doc_number] => 20230386583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => ADAPTIVE POROGRAMMING DELAY SCHEME IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 17/752590 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17007 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17752590 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/752590
Adaptive programming delay scheme in a memory sub-system May 23, 2022 Issued
Array ( [id] => 19328590 [patent_doc_number] => 12046279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Multi-pass programming operation sequence in a memory device [patent_app_type] => utility [patent_app_number] => 17/751179 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 13753 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17751179 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/751179
Multi-pass programming operation sequence in a memory device May 22, 2022 Issued
Array ( [id] => 18789025 [patent_doc_number] => 20230377633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => THREE DIMENSION MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/751445 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4082 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17751445 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/751445
Three dimension memory device capable of improving sensing accuracy in high-speed data sensing operation May 22, 2022 Issued
Array ( [id] => 18789047 [patent_doc_number] => 20230377657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => PUMP SKIP FOR FAST SINGLE-LEVEL CELL NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 17/750938 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18271 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17750938 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/750938
Pump skip for fast single-level cell non-volatile memory May 22, 2022 Issued
Array ( [id] => 19610782 [patent_doc_number] => 12159662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Semiconductor device including write transistor and read transistor disposed on a plane substantially parallel to substrate [patent_app_type] => utility [patent_app_number] => 17/749131 [patent_app_country] => US [patent_app_date] => 2022-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 10319 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17749131 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/749131
Semiconductor device including write transistor and read transistor disposed on a plane substantially parallel to substrate May 18, 2022 Issued
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