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Mushfique Siddique

Examiner (ID: 16359, Phone: (571)270-0424 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
838
Issued Applications
687
Pending Applications
93
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20317957 [patent_doc_number] => 12456512 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-28 [patent_title] => Systems, apparatuses, and methods of using local input/output (LIO) lines for precharging and equalizing digit lines of sense amplifiers [patent_app_type] => utility [patent_app_number] => 17/649173 [patent_app_country] => US [patent_app_date] => 2022-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1226 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17649173 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/649173
Systems, apparatuses, and methods of using local input/output (LIO) lines for precharging and equalizing digit lines of sense amplifiers Jan 26, 2022 Issued
Array ( [id] => 18912857 [patent_doc_number] => 11875841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Memory device with high data bandwidth [patent_app_type] => utility [patent_app_number] => 17/577401 [patent_app_country] => US [patent_app_date] => 2022-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4408 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17577401 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/577401
Memory device with high data bandwidth Jan 17, 2022 Issued
Array ( [id] => 17566301 [patent_doc_number] => 20220130450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => DRAM with inter-section, page-data-copy scheme for low power and wide data access [patent_app_type] => utility [patent_app_number] => 17/568736 [patent_app_country] => US [patent_app_date] => 2022-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4080 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17568736 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/568736
DRAM with inter-section, page-data-copy scheme for low power and wide data access Jan 4, 2022 Issued
Array ( [id] => 19079249 [patent_doc_number] => 11948624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Memory bit cell array including contention-free column reset circuit, and related methods [patent_app_type] => utility [patent_app_number] => 17/560380 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8949 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17560380 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/560380
Memory bit cell array including contention-free column reset circuit, and related methods Dec 22, 2021 Issued
Array ( [id] => 18455857 [patent_doc_number] => 20230197138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => ON-CHIP NOISE GENERATOR FOR POWER BUS [patent_app_type] => utility [patent_app_number] => 17/558512 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9098 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17558512 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/558512
On-chip device testing circuit that generates noise on power bus of memory device Dec 20, 2021 Issued
Array ( [id] => 19182852 [patent_doc_number] => 11989442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Semiconductor integrated circuit, reception device, memory system, and semiconductor storage device for reducing power consumption of equalizer [patent_app_type] => utility [patent_app_number] => 17/644435 [patent_app_country] => US [patent_app_date] => 2021-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8902 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17644435 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/644435
Semiconductor integrated circuit, reception device, memory system, and semiconductor storage device for reducing power consumption of equalizer Dec 14, 2021 Issued
Array ( [id] => 18796714 [patent_doc_number] => 11830540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Circuit for sensing antifuse of DRAMs [patent_app_type] => utility [patent_app_number] => 17/643838 [patent_app_country] => US [patent_app_date] => 2021-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3390 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17643838 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/643838
Circuit for sensing antifuse of DRAMs Dec 11, 2021 Issued
Array ( [id] => 19553830 [patent_doc_number] => 12137552 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-05 [patent_title] => Semiconductor device structure having multiple fuse elements [patent_app_type] => utility [patent_app_number] => 17/545471 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9201 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 340 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17545471 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/545471
Semiconductor device structure having multiple fuse elements Dec 7, 2021 Issued
Array ( [id] => 18423678 [patent_doc_number] => 20230178142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => WORD LINE DRIVER CIRCUITRY INCLUDING SHARED DRIVER GATES, AND ASSOCIATED METHODS, DEVICES, AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/544219 [patent_app_country] => US [patent_app_date] => 2021-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11966 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17544219 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/544219
Word line driver circuitry including shared driver gates, and associated methods, devices, and systems Dec 6, 2021 Issued
Array ( [id] => 17477069 [patent_doc_number] => 20220084573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => METHOD OF REDUCING PROGRAM DISTURBANCE IN MEMORY DEVICE AND MEMORY DEVICE UTILIZING SAME [patent_app_type] => utility [patent_app_number] => 17/539133 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4852 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17539133 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/539133
Method of reducing program disturbance in memory device and memory device utilizing same Nov 29, 2021 Issued
Array ( [id] => 18408659 [patent_doc_number] => 20230170012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => IN-MEMORY COMPUTE SRAM WITH INTEGRATED TOGGLE/COPY OPERATION AND RECONFIGURABLE LOGIC OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/538478 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16904 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17538478 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/538478
IN-MEMORY COMPUTE SRAM WITH INTEGRATED TOGGLE/COPY OPERATION AND RECONFIGURABLE LOGIC OPERATIONS Nov 29, 2021 Pending
Array ( [id] => 17629623 [patent_doc_number] => 20220164638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => METHODS AND APPARATUS FOR NEURAL NETWORK ARRAYS [patent_app_type] => utility [patent_app_number] => 17/535510 [patent_app_country] => US [patent_app_date] => 2021-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10721 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17535510 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/535510
METHODS AND APPARATUS FOR NEURAL NETWORK ARRAYS Nov 23, 2021 Pending
Array ( [id] => 17629623 [patent_doc_number] => 20220164638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-26 [patent_title] => METHODS AND APPARATUS FOR NEURAL NETWORK ARRAYS [patent_app_type] => utility [patent_app_number] => 17/535510 [patent_app_country] => US [patent_app_date] => 2021-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10721 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17535510 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/535510
METHODS AND APPARATUS FOR NEURAL NETWORK ARRAYS Nov 23, 2021 Pending
Array ( [id] => 19229395 [patent_doc_number] => 12009036 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => NAND flash memory device and method of reducing program disturb thereof [patent_app_type] => utility [patent_app_number] => 17/529567 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 13143 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529567 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/529567
NAND flash memory device and method of reducing program disturb thereof Nov 17, 2021 Issued
Array ( [id] => 19046461 [patent_doc_number] => 11935580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => System cache peak power management [patent_app_type] => utility [patent_app_number] => 17/530095 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5627 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530095 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/530095
System cache peak power management Nov 17, 2021 Issued
Array ( [id] => 18379435 [patent_doc_number] => 20230154524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => DDR SDRAM signal calibration device and method [patent_app_type] => utility [patent_app_number] => 17/528208 [patent_app_country] => US [patent_app_date] => 2021-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3658 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17528208 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/528208
DDR SDRAM signal calibration device and method Nov 16, 2021 Issued
Array ( [id] => 18912856 [patent_doc_number] => 11875840 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Semiconductor device performing in-memory processing and operation method thereof [patent_app_type] => utility [patent_app_number] => 17/527908 [patent_app_country] => US [patent_app_date] => 2021-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4037 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17527908 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/527908
Semiconductor device performing in-memory processing and operation method thereof Nov 15, 2021 Issued
Array ( [id] => 18364958 [patent_doc_number] => 20230146549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => SYSTEMS AND METHODS FOR STAGGERING READ OPERATION OF SUB-BLOCKS [patent_app_type] => utility [patent_app_number] => 17/522414 [patent_app_country] => US [patent_app_date] => 2021-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10630 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17522414 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/522414
Systems and methods for staggering read operation of sub-blocks Nov 8, 2021 Issued
Array ( [id] => 18669708 [patent_doc_number] => 11776618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Memory device with in-memory searching array and operation method thereof for implementing finite state machine [patent_app_type] => utility [patent_app_number] => 17/520749 [patent_app_country] => US [patent_app_date] => 2021-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3874 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17520749 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/520749
Memory device with in-memory searching array and operation method thereof for implementing finite state machine Nov 7, 2021 Issued
Array ( [id] => 17676367 [patent_doc_number] => 20220189534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => ELECTRONIC DEVICE FOR PERFORMING SMART REFRESH OPERATION [patent_app_type] => utility [patent_app_number] => 17/521331 [patent_app_country] => US [patent_app_date] => 2021-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17531 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17521331 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/521331
Memory device for performing smart refresh operation and memory system including the same Nov 7, 2021 Issued
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