Search

Mushfique Siddique

Examiner (ID: 16359, Phone: (571)270-0424 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
838
Issued Applications
687
Pending Applications
93
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17463431 [patent_doc_number] => 20220076737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => ANALOG IN-MEMORY COMPUTING BASED INFERENCE ACCELERATOR [patent_app_type] => utility [patent_app_number] => 17/447131 [patent_app_country] => US [patent_app_date] => 2021-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16534 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17447131 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/447131
Analog in-memory computing based inference accelerator Sep 7, 2021 Issued
Array ( [id] => 18225787 [patent_doc_number] => 20230064781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => DYNAMIC BUFFER LIMIT FOR AT-RISK DATA [patent_app_type] => utility [patent_app_number] => 17/462870 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17462870 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/462870
Dynamic buffer limit for at-risk data Aug 30, 2021 Issued
Array ( [id] => 17295189 [patent_doc_number] => 20210391028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => IMPEDANCE CALIBRATION VIA A NUMBER OF CALIBRATION CIRCUITS, AND ASSOCIATED METHODS, DEVICES AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/446559 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8630 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446559 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/446559
Impedance calibration via a number of calibration circuits, and associated methods, devices and systems Aug 30, 2021 Issued
Array ( [id] => 18857042 [patent_doc_number] => 11854633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Anti-fuse memory cell state detection circuit and memory [patent_app_type] => utility [patent_app_number] => 17/446289 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5035 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 340 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446289 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/446289
Anti-fuse memory cell state detection circuit and memory Aug 26, 2021 Issued
Array ( [id] => 18387077 [patent_doc_number] => 11657866 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => QED shifter for a memory device [patent_app_type] => utility [patent_app_number] => 17/459722 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5657 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459722 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/459722
QED shifter for a memory device Aug 26, 2021 Issued
Array ( [id] => 18225601 [patent_doc_number] => 20230064595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/459624 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13921 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459624 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/459624
SRAM with tracking circuitry for reducing active power Aug 26, 2021 Issued
Array ( [id] => 18751302 [patent_doc_number] => 11810620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => Semiconductor storage device [patent_app_type] => utility [patent_app_number] => 17/458067 [patent_app_country] => US [patent_app_date] => 2021-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 13320 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17458067 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/458067
Semiconductor storage device Aug 25, 2021 Issued
Array ( [id] => 18190437 [patent_doc_number] => 11581038 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Semiconductor device for selectively performing isolation function and layout displacement method thereof [patent_app_type] => utility [patent_app_number] => 17/412588 [patent_app_country] => US [patent_app_date] => 2021-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 12513 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17412588 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/412588
Semiconductor device for selectively performing isolation function and layout displacement method thereof Aug 25, 2021 Issued
Array ( [id] => 17870465 [patent_doc_number] => 20220293202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => VEHICLE MEMORY SYSTEM BASED ON 3D MEMORY AND METHOD OPERATING THEREOF [patent_app_type] => utility [patent_app_number] => 17/411547 [patent_app_country] => US [patent_app_date] => 2021-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4308 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17411547 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/411547
Vehicle memory system based on 3D memory and method operating thereof Aug 24, 2021 Issued
Array ( [id] => 18494057 [patent_doc_number] => 11699478 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-11 [patent_title] => Semiconductor memory device in which data writing to cells is controlled using program pulses [patent_app_type] => utility [patent_app_number] => 17/445643 [patent_app_country] => US [patent_app_date] => 2021-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 25131 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 611 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17445643 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/445643
Semiconductor memory device in which data writing to cells is controlled using program pulses Aug 22, 2021 Issued
Array ( [id] => 17302748 [patent_doc_number] => 20210398587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => DATA WRITING METHOD [patent_app_type] => utility [patent_app_number] => 17/408603 [patent_app_country] => US [patent_app_date] => 2021-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6136 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17408603 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/408603
Data writing method Aug 22, 2021 Issued
Array ( [id] => 18387084 [patent_doc_number] => 11657873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Non-volatile static random access memory (nvSRAM) with multiple magnetic tunnel junction cells [patent_app_type] => utility [patent_app_number] => 17/409341 [patent_app_country] => US [patent_app_date] => 2021-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9930 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17409341 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/409341
Non-volatile static random access memory (nvSRAM) with multiple magnetic tunnel junction cells Aug 22, 2021 Issued
Array ( [id] => 18607845 [patent_doc_number] => 11749321 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Multi-stage bit line pre-charge [patent_app_type] => utility [patent_app_number] => 17/408567 [patent_app_country] => US [patent_app_date] => 2021-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4150 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17408567 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/408567
Multi-stage bit line pre-charge Aug 22, 2021 Issued
Array ( [id] => 17833357 [patent_doc_number] => 20220270661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/408454 [patent_app_country] => US [patent_app_date] => 2021-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17408454 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/408454
Memory device for reducing row hammer disturbance and a method of refreshing the same Aug 21, 2021 Issued
Array ( [id] => 18935214 [patent_doc_number] => 11887652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Control circuit and delay circuit [patent_app_type] => utility [patent_app_number] => 17/404246 [patent_app_country] => US [patent_app_date] => 2021-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 54 [patent_no_of_words] => 23823 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17404246 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/404246
Control circuit and delay circuit Aug 16, 2021 Issued
Array ( [id] => 18304244 [patent_doc_number] => 11626156 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Compute-in-memory (CIM) bit cell circuits each disposed in an orientation of a cim bit cell circuit layout including a read word line (RWL) circuit in a cim bit cell array circuit [patent_app_type] => utility [patent_app_number] => 17/404378 [patent_app_country] => US [patent_app_date] => 2021-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12352 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17404378 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/404378
Compute-in-memory (CIM) bit cell circuits each disposed in an orientation of a cim bit cell circuit layout including a read word line (RWL) circuit in a cim bit cell array circuit Aug 16, 2021 Issued
Array ( [id] => 17302747 [patent_doc_number] => 20210398586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT AND MEMORY [patent_app_type] => utility [patent_app_number] => 17/396688 [patent_app_country] => US [patent_app_date] => 2021-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17261 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17396688 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/396688
Memory integrated circuit with local amplifier module and local read-write conversion module to improve operation speed and reduce number of data lines Aug 6, 2021 Issued
Array ( [id] => 18578711 [patent_doc_number] => 11735250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Sense amplifier activation timing scheme to suppress disturbance in memory cells of dram memory device [patent_app_type] => utility [patent_app_number] => 17/395964 [patent_app_country] => US [patent_app_date] => 2021-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7732 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17395964 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/395964
Sense amplifier activation timing scheme to suppress disturbance in memory cells of dram memory device Aug 5, 2021 Issued
Array ( [id] => 18174960 [patent_doc_number] => 11574677 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Nonvolatile memory device with vertical string including semiconductor and resistance change layers, and method of operating the same [patent_app_type] => utility [patent_app_number] => 17/385263 [patent_app_country] => US [patent_app_date] => 2021-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9254 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17385263 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/385263
Nonvolatile memory device with vertical string including semiconductor and resistance change layers, and method of operating the same Jul 25, 2021 Issued
Array ( [id] => 17833362 [patent_doc_number] => 20220270666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND COLUMN PATH CONTROL CIRCUIT THEREFOR [patent_app_type] => utility [patent_app_number] => 17/443412 [patent_app_country] => US [patent_app_date] => 2021-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4917 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17443412 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/443412
Semiconductor memory device with column path control circuit that controls column path for accessing a core circuit with multiple bank groups and column path control circuit therefor Jul 25, 2021 Issued
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