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Mushfique Siddique

Examiner (ID: 16359, Phone: (571)270-0424 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
838
Issued Applications
687
Pending Applications
93
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18578718 [patent_doc_number] => 11735257 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Memory with high-accuracy reference-free multi-inverter sense circuit and associated sensing method [patent_app_type] => utility [patent_app_number] => 17/380093 [patent_app_country] => US [patent_app_date] => 2021-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 8503 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17380093 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/380093
Memory with high-accuracy reference-free multi-inverter sense circuit and associated sensing method Jul 19, 2021 Issued
Array ( [id] => 18148151 [patent_doc_number] => 20230022008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => MEMORY DEVICE FOR DATA SEARCHING AND DATA SEARCHING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/380056 [patent_app_country] => US [patent_app_date] => 2021-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6053 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17380056 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/380056
Memory device with input circuit, output circuit for performing efficient data searching and comparing within large-sized memory array Jul 19, 2021 Issued
Array ( [id] => 19654253 [patent_doc_number] => 12176053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Wordline system architecture supporting erase operation and I-V characterization [patent_app_type] => utility [patent_app_number] => 17/380688 [patent_app_country] => US [patent_app_date] => 2021-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5487 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17380688 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/380688
Wordline system architecture supporting erase operation and I-V characterization Jul 19, 2021 Issued
Array ( [id] => 18562731 [patent_doc_number] => 11727981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Sense amplifier with digit line multiplexing [patent_app_type] => utility [patent_app_number] => 17/369873 [patent_app_country] => US [patent_app_date] => 2021-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 18401 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17369873 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/369873
Sense amplifier with digit line multiplexing Jul 6, 2021 Issued
Array ( [id] => 18122270 [patent_doc_number] => 20230007872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => METHODS OF REDUCING CLOCK DOMAIN CROSSING TIMING VIOLATIONS, AND RELATED DEVICES AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/369055 [patent_app_country] => US [patent_app_date] => 2021-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8904 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17369055 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/369055
Methods of reducing clock domain crossing timing violations, and related devices and systems Jul 6, 2021 Issued
Array ( [id] => 18112641 [patent_doc_number] => 20230005521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => SINGLE ENDED CURRENT MODE SENSE AMPLIFIER [patent_app_type] => utility [patent_app_number] => 17/367455 [patent_app_country] => US [patent_app_date] => 2021-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10035 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17367455 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/367455
Single ended current mode sense amplifier with feedback inverter Jul 4, 2021 Issued
Array ( [id] => 18507604 [patent_doc_number] => 11705432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding, and related methods and devices [patent_app_type] => utility [patent_app_number] => 17/365741 [patent_app_country] => US [patent_app_date] => 2021-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7950 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17365741 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/365741
Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding, and related methods and devices Jun 30, 2021 Issued
Array ( [id] => 17810591 [patent_doc_number] => 20220262426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => Memory System Capable of Performing a Bit Partitioning Process and an Internal Computation Process [patent_app_type] => utility [patent_app_number] => 17/351280 [patent_app_country] => US [patent_app_date] => 2021-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5282 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17351280 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/351280
Memory system capable of performing a bit partitioning process and an internal computation process Jun 17, 2021 Issued
Array ( [id] => 18415812 [patent_doc_number] => 11670357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Memory system configured to perform a reset on one or more non-volatile memory cells upon transitioning power states [patent_app_type] => utility [patent_app_number] => 17/350757 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 22513 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17350757 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/350757
Memory system configured to perform a reset on one or more non-volatile memory cells upon transitioning power states Jun 16, 2021 Issued
Array ( [id] => 18304242 [patent_doc_number] => 11626154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Quarter match concurrent compensation in a memory system [patent_app_type] => utility [patent_app_number] => 17/350325 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9337 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 324 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17350325 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/350325
Quarter match concurrent compensation in a memory system Jun 16, 2021 Issued
Array ( [id] => 18721258 [patent_doc_number] => 11798610 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Apparatuses and methods for controlling steal rates [patent_app_type] => utility [patent_app_number] => 17/347957 [patent_app_country] => US [patent_app_date] => 2021-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9416 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17347957 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/347957
Apparatuses and methods for controlling steal rates Jun 14, 2021 Issued
Array ( [id] => 17145497 [patent_doc_number] => 20210313510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => MAGNETIC RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 17/346845 [patent_app_country] => US [patent_app_date] => 2021-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10006 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17346845 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/346845
Magnetic random access memory Jun 13, 2021 Issued
Array ( [id] => 17485656 [patent_doc_number] => 20220093160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => METHOD OF COUNTING NUMBER OF CELLS IN NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY DEVICE PERFORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/346171 [patent_app_country] => US [patent_app_date] => 2021-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17818 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17346171 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/346171
Method of counting number of cells in nonvolatile memory device and nonvolatile memory device with cell counter performing the same Jun 10, 2021 Issued
Array ( [id] => 18067351 [patent_doc_number] => 20220398439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-15 [patent_title] => COMPUTE IN MEMORY THREE-DIMENSIONAL NON-VOLATILE NAND MEMORY FOR NEURAL NETWORKS WITH WEIGHT AND INPUT LEVEL EXPANSIONS [patent_app_type] => utility [patent_app_number] => 17/343240 [patent_app_country] => US [patent_app_date] => 2021-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18810 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17343240 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/343240
Compute in memory three-dimensional non-volatile NAND memory for neural networks with weight and input level expansions Jun 8, 2021 Issued
Array ( [id] => 18190432 [patent_doc_number] => 11581033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Sub-sense amplifier layout scheme to reduce area [patent_app_type] => utility [patent_app_number] => 17/342565 [patent_app_country] => US [patent_app_date] => 2021-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4676 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17342565 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/342565
Sub-sense amplifier layout scheme to reduce area Jun 8, 2021 Issued
Array ( [id] => 18205206 [patent_doc_number] => 11587608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Volatile memory device, storage device, and operating method of decreasing a leakage current [patent_app_type] => utility [patent_app_number] => 17/337231 [patent_app_country] => US [patent_app_date] => 2021-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11765 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17337231 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/337231
Volatile memory device, storage device, and operating method of decreasing a leakage current Jun 1, 2021 Issued
Array ( [id] => 18039722 [patent_doc_number] => 20220383939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => MEMORY HAVING FLYING BITLINES FOR IMPROVED BURST MODE READ OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/333638 [patent_app_country] => US [patent_app_date] => 2021-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8033 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17333638 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/333638
Memory having flying bitlines for improved burst mode read operations May 27, 2021 Issued
Array ( [id] => 18639259 [patent_doc_number] => 11763875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Second word line combined with Y-MUX signal in high voltage memory program [patent_app_type] => utility [patent_app_number] => 17/331340 [patent_app_country] => US [patent_app_date] => 2021-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6033 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17331340 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/331340
Second word line combined with Y-MUX signal in high voltage memory program May 25, 2021 Issued
Array ( [id] => 17917175 [patent_doc_number] => 20220319571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => ASYNCHRONOUS MULTI-PLANE INDEPENDENT SCHEME DYNAMIC ANALOG RESOURCE SHARING IN THREE-DIMENSIONAL MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/331226 [patent_app_country] => US [patent_app_date] => 2021-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10954 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17331226 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/331226
Asynchronous multi-plane independent scheme dynamic analog resource sharing in three-dimensional memory devices May 25, 2021 Issued
Array ( [id] => 17262369 [patent_doc_number] => 20210375354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => DATA DESTRUCTION [patent_app_type] => utility [patent_app_number] => 17/325977 [patent_app_country] => US [patent_app_date] => 2021-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14590 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17325977 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/325977
DRAM security erase May 19, 2021 Issued
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