| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 17536449
[patent_doc_number] => 20220115058
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-14
[patent_title] => MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/322078
[patent_app_country] => US
[patent_app_date] => 2021-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11325
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17322078
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/322078 | Memory device including an ovonic threshold switch element and a method of operating thereof | May 16, 2021 | Issued |
Array
(
[id] => 18155932
[patent_doc_number] => 11568921
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-31
[patent_title] => Read-time overhead and power optimizations with command queues in memory device
[patent_app_type] => utility
[patent_app_number] => 17/318579
[patent_app_country] => US
[patent_app_date] => 2021-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 12894
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17318579
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/318579 | Read-time overhead and power optimizations with command queues in memory device | May 11, 2021 | Issued |
Array
(
[id] => 18998932
[patent_doc_number] => 11915786
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-27
[patent_title] => Current control circuit and discharge enable circuit for discharging bit lines of memory device and operation method thereof
[patent_app_type] => utility
[patent_app_number] => 17/307924
[patent_app_country] => US
[patent_app_date] => 2021-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 6682
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17307924
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/307924 | Current control circuit and discharge enable circuit for discharging bit lines of memory device and operation method thereof | May 3, 2021 | Issued |
Array
(
[id] => 17985734
[patent_doc_number] => 20220351771
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-03
[patent_title] => VARYING A TIME AVERAGE FOR FEEDBACK OF A MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 17/243444
[patent_app_country] => US
[patent_app_date] => 2021-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12102
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17243444
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/243444 | Varying a time average for feedback of a memory system | Apr 27, 2021 | Issued |
Array
(
[id] => 17948988
[patent_doc_number] => 20220336007
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-20
[patent_title] => APPARATUSES AND METHODS OF POWER SUPPLY CONTROL FOR TEMPERATURE COMPENSATED SENSE AMPLIFIERS
[patent_app_type] => utility
[patent_app_number] => 17/235775
[patent_app_country] => US
[patent_app_date] => 2021-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7254
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17235775
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/235775 | Apparatuses and methods of power supply control for temperature compensated sense amplifiers | Apr 19, 2021 | Issued |
Array
(
[id] => 17948987
[patent_doc_number] => 20220336006
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-20
[patent_title] => FAST INTERVAL READ SETUP FOR 3D MEMORY
[patent_app_type] => utility
[patent_app_number] => 17/234236
[patent_app_country] => US
[patent_app_date] => 2021-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10266
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17234236
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/234236 | Fast interval read setup for 3D memory | Apr 18, 2021 | Issued |
Array
(
[id] => 19740944
[patent_doc_number] => 12217783
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-04
[patent_title] => Semiconductor storage with two power source paths
[patent_app_type] => utility
[patent_app_number] => 17/999234
[patent_app_country] => US
[patent_app_date] => 2021-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 18
[patent_no_of_words] => 8724
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17999234
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/999234 | Semiconductor storage with two power source paths | Apr 18, 2021 | Issued |
Array
(
[id] => 17463421
[patent_doc_number] => 20220076727
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-10
[patent_title] => NON-VOLATILE MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/233858
[patent_app_country] => US
[patent_app_date] => 2021-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13837
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17233858
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/233858 | Non-volatile memory device which utilizes a pulse applied to a bit line and/or a common source line between read operations to reduce noise | Apr 18, 2021 | Issued |
Array
(
[id] => 19627162
[patent_doc_number] => 12166011
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2024-12-10
[patent_title] => Method of forming an artificial intelligence processor with three-dimensional stacked memory
[patent_app_type] => utility
[patent_app_number] => 17/230890
[patent_app_country] => US
[patent_app_date] => 2021-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 29
[patent_no_of_words] => 13190
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17230890
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/230890 | Method of forming an artificial intelligence processor with three-dimensional stacked memory | Apr 13, 2021 | Issued |
Array
(
[id] => 17615089
[patent_doc_number] => 20220157369
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-19
[patent_title] => SENSE AMPLIFYING CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/227741
[patent_app_country] => US
[patent_app_date] => 2021-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8075
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17227741
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/227741 | Sense amplifying circuit of semiconductor memory device for offset cancellation operation | Apr 11, 2021 | Issued |
Array
(
[id] => 17158242
[patent_doc_number] => 20210319293
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-14
[patent_title] => NEUROMORPHIC DEVICE AND OPERATING METHOD OF THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/224575
[patent_app_country] => US
[patent_app_date] => 2021-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7478
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17224575
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/224575 | NEUROMORPHIC DEVICE AND OPERATING METHOD OF THE SAME | Apr 6, 2021 | Pending |
Array
(
[id] => 17158242
[patent_doc_number] => 20210319293
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-14
[patent_title] => NEUROMORPHIC DEVICE AND OPERATING METHOD OF THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/224575
[patent_app_country] => US
[patent_app_date] => 2021-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7478
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17224575
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/224575 | NEUROMORPHIC DEVICE AND OPERATING METHOD OF THE SAME | Apr 6, 2021 | Pending |
Array
(
[id] => 17917185
[patent_doc_number] => 20220319581
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-06
[patent_title] => MEMORY DEVICES IMPLEMENTING DATA-ACCESS SCHEMES FOR DIGIT LINES PROXIMATE TO EDGES OF COLUMN PLANES, AND RELATED DEVICES, SYSTEMS, AND METHODS
[patent_app_type] => utility
[patent_app_number] => 17/220110
[patent_app_country] => US
[patent_app_date] => 2021-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11284
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17220110
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/220110 | Memory devices implementing data-access schemes for digit lines proximate to edges of column planes, and related devices, systems, and methods | Mar 31, 2021 | Issued |
Array
(
[id] => 17878366
[patent_doc_number] => 11450387
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-09-20
[patent_title] => Method of controlling internal address for a serial nor flash memory
[patent_app_type] => utility
[patent_app_number] => 17/211060
[patent_app_country] => US
[patent_app_date] => 2021-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 5970
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 248
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17211060
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/211060 | Method of controlling internal address for a serial nor flash memory | Mar 23, 2021 | Issued |
Array
(
[id] => 19780617
[patent_doc_number] => 12229652
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-18
[patent_title] => Two-terminal metastable mixed-conductor memristive devices
[patent_app_type] => utility
[patent_app_number] => 17/208370
[patent_app_country] => US
[patent_app_date] => 2021-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 8103
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17208370
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/208370 | Two-terminal metastable mixed-conductor memristive devices | Mar 21, 2021 | Issued |
Array
(
[id] => 17779844
[patent_doc_number] => 20220246194
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-04
[patent_title] => FLASH MEMORY STORAGE APPARATUS AND A BIASING METHOD THEREOF, WHICH CAN REDUCE A GATE INDUCED DRAIN LEAKAGE (GIDL) AND IMPROVE RELIABILITY OF MEMORY CELLS
[patent_app_type] => utility
[patent_app_number] => 17/204955
[patent_app_country] => US
[patent_app_date] => 2021-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2809
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17204955
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/204955 | FLASH MEMORY STORAGE APPARATUS AND A BIASING METHOD THEREOF, WHICH CAN REDUCE A GATE INDUCED DRAIN LEAKAGE (GIDL) AND IMPROVE RELIABILITY OF MEMORY CELLS | Mar 17, 2021 | Abandoned |
Array
(
[id] => 17978412
[patent_doc_number] => 11495284
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-08
[patent_title] => Memory device including bitline sense amplifier and operating method thereof
[patent_app_type] => utility
[patent_app_number] => 17/202466
[patent_app_country] => US
[patent_app_date] => 2021-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 11894
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17202466
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/202466 | Memory device including bitline sense amplifier and operating method thereof | Mar 15, 2021 | Issued |
Array
(
[id] => 17416810
[patent_doc_number] => 20220051714
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-17
[patent_title] => NONVOLATILE MEMORY DEVICE AND READ METHOD OF NONVOLATILE MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/200557
[patent_app_country] => US
[patent_app_date] => 2021-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20068
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17200557
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/200557 | Nonvolatile memory device with page buffer circuit supporting read operation of improved reliabilty | Mar 11, 2021 | Issued |
Array
(
[id] => 17040387
[patent_doc_number] => 20210257023
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-19
[patent_title] => Set-While-Verify Circuit And Reset-While Verify Circuit For Resistive Random Access Memory Cells
[patent_app_type] => utility
[patent_app_number] => 17/199243
[patent_app_country] => US
[patent_app_date] => 2021-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11421
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17199243
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/199243 | Set-while-verify circuit and reset-while verify circuit for resistive random access memory cells | Mar 10, 2021 | Issued |
Array
(
[id] => 17978420
[patent_doc_number] => 11495292
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-08
[patent_title] => Resistive random access memory device with three-dimensional cross-point structure and method of operating the same
[patent_app_type] => utility
[patent_app_number] => 17/195994
[patent_app_country] => US
[patent_app_date] => 2021-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 25
[patent_no_of_words] => 7457
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17195994
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/195994 | Resistive random access memory device with three-dimensional cross-point structure and method of operating the same | Mar 8, 2021 | Issued |