Search

Mushfique Siddique

Examiner (ID: 1672, Phone: (571)270-0424 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
886
Issued Applications
722
Pending Applications
91
Abandoned Applications
88

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17833357 [patent_doc_number] => 20220270661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/408454 [patent_app_country] => US [patent_app_date] => 2021-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17408454 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/408454
Memory device for reducing row hammer disturbance and a method of refreshing the same Aug 21, 2021 Issued
Array ( [id] => 18304244 [patent_doc_number] => 11626156 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Compute-in-memory (CIM) bit cell circuits each disposed in an orientation of a cim bit cell circuit layout including a read word line (RWL) circuit in a cim bit cell array circuit [patent_app_type] => utility [patent_app_number] => 17/404378 [patent_app_country] => US [patent_app_date] => 2021-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12352 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17404378 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/404378
Compute-in-memory (CIM) bit cell circuits each disposed in an orientation of a cim bit cell circuit layout including a read word line (RWL) circuit in a cim bit cell array circuit Aug 16, 2021 Issued
Array ( [id] => 18935214 [patent_doc_number] => 11887652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Control circuit and delay circuit [patent_app_type] => utility [patent_app_number] => 17/404246 [patent_app_country] => US [patent_app_date] => 2021-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 54 [patent_no_of_words] => 23823 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17404246 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/404246
Control circuit and delay circuit Aug 16, 2021 Issued
Array ( [id] => 17412296 [patent_doc_number] => 20220047200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => INFORMATION PROCESSING CIRCUIT AND INFORMATION PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 17/402263 [patent_app_country] => US [patent_app_date] => 2021-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10647 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17402263 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/402263
INFORMATION PROCESSING CIRCUIT AND INFORMATION PROCESSING METHOD Aug 12, 2021 Pending
Array ( [id] => 17302747 [patent_doc_number] => 20210398586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT AND MEMORY [patent_app_type] => utility [patent_app_number] => 17/396688 [patent_app_country] => US [patent_app_date] => 2021-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17261 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17396688 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/396688
Memory integrated circuit with local amplifier module and local read-write conversion module to improve operation speed and reduce number of data lines Aug 6, 2021 Issued
Array ( [id] => 18578711 [patent_doc_number] => 11735250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Sense amplifier activation timing scheme to suppress disturbance in memory cells of dram memory device [patent_app_type] => utility [patent_app_number] => 17/395964 [patent_app_country] => US [patent_app_date] => 2021-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7732 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17395964 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/395964
Sense amplifier activation timing scheme to suppress disturbance in memory cells of dram memory device Aug 5, 2021 Issued
Array ( [id] => 18174960 [patent_doc_number] => 11574677 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Nonvolatile memory device with vertical string including semiconductor and resistance change layers, and method of operating the same [patent_app_type] => utility [patent_app_number] => 17/385263 [patent_app_country] => US [patent_app_date] => 2021-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9254 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17385263 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/385263
Nonvolatile memory device with vertical string including semiconductor and resistance change layers, and method of operating the same Jul 25, 2021 Issued
Array ( [id] => 17833362 [patent_doc_number] => 20220270666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND COLUMN PATH CONTROL CIRCUIT THEREFOR [patent_app_type] => utility [patent_app_number] => 17/443412 [patent_app_country] => US [patent_app_date] => 2021-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4917 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17443412 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/443412
Semiconductor memory device with column path control circuit that controls column path for accessing a core circuit with multiple bank groups and column path control circuit therefor Jul 25, 2021 Issued
Array ( [id] => 18148151 [patent_doc_number] => 20230022008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => MEMORY DEVICE FOR DATA SEARCHING AND DATA SEARCHING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/380056 [patent_app_country] => US [patent_app_date] => 2021-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6053 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17380056 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/380056
Memory device with input circuit, output circuit for performing efficient data searching and comparing within large-sized memory array Jul 19, 2021 Issued
Array ( [id] => 18578718 [patent_doc_number] => 11735257 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Memory with high-accuracy reference-free multi-inverter sense circuit and associated sensing method [patent_app_type] => utility [patent_app_number] => 17/380093 [patent_app_country] => US [patent_app_date] => 2021-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 8503 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17380093 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/380093
Memory with high-accuracy reference-free multi-inverter sense circuit and associated sensing method Jul 19, 2021 Issued
Array ( [id] => 19654253 [patent_doc_number] => 12176053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Wordline system architecture supporting erase operation and I-V characterization [patent_app_type] => utility [patent_app_number] => 17/380688 [patent_app_country] => US [patent_app_date] => 2021-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5487 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17380688 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/380688
Wordline system architecture supporting erase operation and I-V characterization Jul 19, 2021 Issued
Array ( [id] => 18562731 [patent_doc_number] => 11727981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Sense amplifier with digit line multiplexing [patent_app_type] => utility [patent_app_number] => 17/369873 [patent_app_country] => US [patent_app_date] => 2021-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 18401 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17369873 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/369873
Sense amplifier with digit line multiplexing Jul 6, 2021 Issued
Array ( [id] => 18122270 [patent_doc_number] => 20230007872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => METHODS OF REDUCING CLOCK DOMAIN CROSSING TIMING VIOLATIONS, AND RELATED DEVICES AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/369055 [patent_app_country] => US [patent_app_date] => 2021-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8904 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17369055 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/369055
Methods of reducing clock domain crossing timing violations, and related devices and systems Jul 6, 2021 Issued
Array ( [id] => 18112641 [patent_doc_number] => 20230005521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => SINGLE ENDED CURRENT MODE SENSE AMPLIFIER [patent_app_type] => utility [patent_app_number] => 17/367455 [patent_app_country] => US [patent_app_date] => 2021-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10035 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17367455 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/367455
Single ended current mode sense amplifier with feedback inverter Jul 4, 2021 Issued
Array ( [id] => 18507604 [patent_doc_number] => 11705432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-18 [patent_title] => Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding, and related methods and devices [patent_app_type] => utility [patent_app_number] => 17/365741 [patent_app_country] => US [patent_app_date] => 2021-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7950 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17365741 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/365741
Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding, and related methods and devices Jun 30, 2021 Issued
Array ( [id] => 17810591 [patent_doc_number] => 20220262426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => Memory System Capable of Performing a Bit Partitioning Process and an Internal Computation Process [patent_app_type] => utility [patent_app_number] => 17/351280 [patent_app_country] => US [patent_app_date] => 2021-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5282 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17351280 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/351280
Memory system capable of performing a bit partitioning process and an internal computation process Jun 17, 2021 Issued
Array ( [id] => 18304242 [patent_doc_number] => 11626154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Quarter match concurrent compensation in a memory system [patent_app_type] => utility [patent_app_number] => 17/350325 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9337 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 324 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17350325 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/350325
Quarter match concurrent compensation in a memory system Jun 16, 2021 Issued
Array ( [id] => 18415812 [patent_doc_number] => 11670357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Memory system configured to perform a reset on one or more non-volatile memory cells upon transitioning power states [patent_app_type] => utility [patent_app_number] => 17/350757 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 22513 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17350757 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/350757
Memory system configured to perform a reset on one or more non-volatile memory cells upon transitioning power states Jun 16, 2021 Issued
Array ( [id] => 18721258 [patent_doc_number] => 11798610 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Apparatuses and methods for controlling steal rates [patent_app_type] => utility [patent_app_number] => 17/347957 [patent_app_country] => US [patent_app_date] => 2021-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9416 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17347957 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/347957
Apparatuses and methods for controlling steal rates Jun 14, 2021 Issued
Array ( [id] => 17145497 [patent_doc_number] => 20210313510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => MAGNETIC RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 17/346845 [patent_app_country] => US [patent_app_date] => 2021-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10006 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17346845 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/346845
Magnetic random access memory Jun 13, 2021 Issued
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