| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 17485656
[patent_doc_number] => 20220093160
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-24
[patent_title] => METHOD OF COUNTING NUMBER OF CELLS IN NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY DEVICE PERFORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/346171
[patent_app_country] => US
[patent_app_date] => 2021-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17818
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17346171
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/346171 | Method of counting number of cells in nonvolatile memory device and nonvolatile memory device with cell counter performing the same | Jun 10, 2021 | Issued |
Array
(
[id] => 18067351
[patent_doc_number] => 20220398439
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-15
[patent_title] => COMPUTE IN MEMORY THREE-DIMENSIONAL NON-VOLATILE NAND MEMORY FOR NEURAL NETWORKS WITH WEIGHT AND INPUT LEVEL EXPANSIONS
[patent_app_type] => utility
[patent_app_number] => 17/343240
[patent_app_country] => US
[patent_app_date] => 2021-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18810
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 265
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17343240
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/343240 | Compute in memory three-dimensional non-volatile NAND memory for neural networks with weight and input level expansions | Jun 8, 2021 | Issued |
Array
(
[id] => 18190432
[patent_doc_number] => 11581033
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-14
[patent_title] => Sub-sense amplifier layout scheme to reduce area
[patent_app_type] => utility
[patent_app_number] => 17/342565
[patent_app_country] => US
[patent_app_date] => 2021-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 4676
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 261
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17342565
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/342565 | Sub-sense amplifier layout scheme to reduce area | Jun 8, 2021 | Issued |
Array
(
[id] => 18205206
[patent_doc_number] => 11587608
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-21
[patent_title] => Volatile memory device, storage device, and operating method of decreasing a leakage current
[patent_app_type] => utility
[patent_app_number] => 17/337231
[patent_app_country] => US
[patent_app_date] => 2021-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 11765
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17337231
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/337231 | Volatile memory device, storage device, and operating method of decreasing a leakage current | Jun 1, 2021 | Issued |
Array
(
[id] => 18039722
[patent_doc_number] => 20220383939
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-01
[patent_title] => MEMORY HAVING FLYING BITLINES FOR IMPROVED BURST MODE READ OPERATIONS
[patent_app_type] => utility
[patent_app_number] => 17/333638
[patent_app_country] => US
[patent_app_date] => 2021-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8033
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17333638
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/333638 | Memory having flying bitlines for improved burst mode read operations | May 27, 2021 | Issued |
Array
(
[id] => 17917175
[patent_doc_number] => 20220319571
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-06
[patent_title] => ASYNCHRONOUS MULTI-PLANE INDEPENDENT SCHEME DYNAMIC ANALOG RESOURCE SHARING IN THREE-DIMENSIONAL MEMORY DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/331226
[patent_app_country] => US
[patent_app_date] => 2021-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10954
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17331226
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/331226 | Asynchronous multi-plane independent scheme dynamic analog resource sharing in three-dimensional memory devices | May 25, 2021 | Issued |
Array
(
[id] => 18639259
[patent_doc_number] => 11763875
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-09-19
[patent_title] => Second word line combined with Y-MUX signal in high voltage memory program
[patent_app_type] => utility
[patent_app_number] => 17/331340
[patent_app_country] => US
[patent_app_date] => 2021-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6033
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17331340
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/331340 | Second word line combined with Y-MUX signal in high voltage memory program | May 25, 2021 | Issued |
Array
(
[id] => 17262369
[patent_doc_number] => 20210375354
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-02
[patent_title] => DATA DESTRUCTION
[patent_app_type] => utility
[patent_app_number] => 17/325977
[patent_app_country] => US
[patent_app_date] => 2021-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14590
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17325977
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/325977 | DRAM security erase | May 19, 2021 | Issued |
Array
(
[id] => 17536449
[patent_doc_number] => 20220115058
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-14
[patent_title] => MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/322078
[patent_app_country] => US
[patent_app_date] => 2021-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11325
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17322078
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/322078 | Memory device including an ovonic threshold switch element and a method of operating thereof | May 16, 2021 | Issued |
Array
(
[id] => 18155932
[patent_doc_number] => 11568921
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-31
[patent_title] => Read-time overhead and power optimizations with command queues in memory device
[patent_app_type] => utility
[patent_app_number] => 17/318579
[patent_app_country] => US
[patent_app_date] => 2021-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 12894
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17318579
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/318579 | Read-time overhead and power optimizations with command queues in memory device | May 11, 2021 | Issued |
Array
(
[id] => 18998932
[patent_doc_number] => 11915786
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-27
[patent_title] => Current control circuit and discharge enable circuit for discharging bit lines of memory device and operation method thereof
[patent_app_type] => utility
[patent_app_number] => 17/307924
[patent_app_country] => US
[patent_app_date] => 2021-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 6682
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17307924
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/307924 | Current control circuit and discharge enable circuit for discharging bit lines of memory device and operation method thereof | May 3, 2021 | Issued |
Array
(
[id] => 17985734
[patent_doc_number] => 20220351771
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-03
[patent_title] => VARYING A TIME AVERAGE FOR FEEDBACK OF A MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 17/243444
[patent_app_country] => US
[patent_app_date] => 2021-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12102
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17243444
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/243444 | Varying a time average for feedback of a memory system | Apr 27, 2021 | Issued |
Array
(
[id] => 17948988
[patent_doc_number] => 20220336007
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-20
[patent_title] => APPARATUSES AND METHODS OF POWER SUPPLY CONTROL FOR TEMPERATURE COMPENSATED SENSE AMPLIFIERS
[patent_app_type] => utility
[patent_app_number] => 17/235775
[patent_app_country] => US
[patent_app_date] => 2021-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7254
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17235775
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/235775 | Apparatuses and methods of power supply control for temperature compensated sense amplifiers | Apr 19, 2021 | Issued |
Array
(
[id] => 17463421
[patent_doc_number] => 20220076727
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-10
[patent_title] => NON-VOLATILE MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/233858
[patent_app_country] => US
[patent_app_date] => 2021-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13837
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17233858
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/233858 | Non-volatile memory device which utilizes a pulse applied to a bit line and/or a common source line between read operations to reduce noise | Apr 18, 2021 | Issued |
Array
(
[id] => 17948987
[patent_doc_number] => 20220336006
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-20
[patent_title] => FAST INTERVAL READ SETUP FOR 3D MEMORY
[patent_app_type] => utility
[patent_app_number] => 17/234236
[patent_app_country] => US
[patent_app_date] => 2021-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10266
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17234236
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/234236 | Fast interval read setup for 3D memory | Apr 18, 2021 | Issued |
Array
(
[id] => 19740944
[patent_doc_number] => 12217783
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-04
[patent_title] => Semiconductor storage with two power source paths
[patent_app_type] => utility
[patent_app_number] => 17/999234
[patent_app_country] => US
[patent_app_date] => 2021-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 18
[patent_no_of_words] => 8724
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17999234
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/999234 | Semiconductor storage with two power source paths | Apr 18, 2021 | Issued |
Array
(
[id] => 19627162
[patent_doc_number] => 12166011
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2024-12-10
[patent_title] => Method of forming an artificial intelligence processor with three-dimensional stacked memory
[patent_app_type] => utility
[patent_app_number] => 17/230890
[patent_app_country] => US
[patent_app_date] => 2021-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 29
[patent_no_of_words] => 13190
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17230890
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/230890 | Method of forming an artificial intelligence processor with three-dimensional stacked memory | Apr 13, 2021 | Issued |
Array
(
[id] => 17615089
[patent_doc_number] => 20220157369
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-19
[patent_title] => SENSE AMPLIFYING CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/227741
[patent_app_country] => US
[patent_app_date] => 2021-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8075
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17227741
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/227741 | Sense amplifying circuit of semiconductor memory device for offset cancellation operation | Apr 11, 2021 | Issued |
Array
(
[id] => 20455093
[patent_doc_number] => 12518147
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-01-06
[patent_title] => Neuromorphic device and operating method of the same
[patent_app_type] => utility
[patent_app_number] => 17/224575
[patent_app_country] => US
[patent_app_date] => 2021-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 18
[patent_no_of_words] => 2217
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17224575
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/224575 | Neuromorphic device and operating method of the same | Apr 6, 2021 | Issued |
Array
(
[id] => 17917185
[patent_doc_number] => 20220319581
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-06
[patent_title] => MEMORY DEVICES IMPLEMENTING DATA-ACCESS SCHEMES FOR DIGIT LINES PROXIMATE TO EDGES OF COLUMN PLANES, AND RELATED DEVICES, SYSTEMS, AND METHODS
[patent_app_type] => utility
[patent_app_number] => 17/220110
[patent_app_country] => US
[patent_app_date] => 2021-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11284
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17220110
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/220110 | Memory devices implementing data-access schemes for digit lines proximate to edges of column planes, and related devices, systems, and methods | Mar 31, 2021 | Issued |