Search

Mushfique Siddique

Examiner (ID: 16359, Phone: (571)270-0424 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
838
Issued Applications
687
Pending Applications
93
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18031764 [patent_doc_number] => 11514959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-29 [patent_title] => Memory device capable of adjusting clock signal based on operating speed and propagation delay of command/address signal [patent_app_type] => utility [patent_app_number] => 17/193955 [patent_app_country] => US [patent_app_date] => 2021-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5578 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17193955 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/193955
Memory device capable of adjusting clock signal based on operating speed and propagation delay of command/address signal Mar 4, 2021 Issued
Array ( [id] => 17854902 [patent_doc_number] => 20220284945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => SEARCHABLE ARRAY CIRCUITS WITH LOAD-MATCHED SIGNALS FOR REDUCED HIT SIGNAL TIMING MARGINS AND RELATED METHODS [patent_app_type] => utility [patent_app_number] => 17/249464 [patent_app_country] => US [patent_app_date] => 2021-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10572 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17249464 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/249464
Searchable array circuits with load-matched signals for reduced hit signal timing margins and related methods Mar 1, 2021 Issued
Array ( [id] => 17833364 [patent_doc_number] => 20220270668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => EFFICIENT IO SECTION BREAK SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 17/184345 [patent_app_country] => US [patent_app_date] => 2021-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6954 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17184345 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/184345
Systems, devices, and methods for efficient usage of IO section breaks in memory devices Feb 23, 2021 Issued
Array ( [id] => 18371627 [patent_doc_number] => 11651808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-16 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/181035 [patent_app_country] => US [patent_app_date] => 2021-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 37 [patent_no_of_words] => 15653 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17181035 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/181035
Semiconductor memory device Feb 21, 2021 Issued
Array ( [id] => 17551330 [patent_doc_number] => 20220122672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => Power Reduction During Open and Erased Block Reads of Memory [patent_app_type] => utility [patent_app_number] => 17/173805 [patent_app_country] => US [patent_app_date] => 2021-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4921 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17173805 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/173805
Power reduction during open and erased block reads of memory based on the position of last written word line of a memory block Feb 10, 2021 Issued
Array ( [id] => 16903289 [patent_doc_number] => 20210182205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => SEMICONDUCTOR MEMORY [patent_app_type] => utility [patent_app_number] => 17/171214 [patent_app_country] => US [patent_app_date] => 2021-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5721 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17171214 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/171214
Semiconductor memory device with mapping factor generating unit for improving reliability Feb 8, 2021 Issued
Array ( [id] => 17825579 [patent_doc_number] => 11430531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Read integration time calibration for non-volatile storage [patent_app_type] => utility [patent_app_number] => 17/171637 [patent_app_country] => US [patent_app_date] => 2021-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 21400 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17171637 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/171637
Read integration time calibration for non-volatile storage Feb 8, 2021 Issued
Array ( [id] => 16858106 [patent_doc_number] => 20210158851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR ANALOG ROW ACCESS RATE DETERMINATION [patent_app_type] => utility [patent_app_number] => 17/170616 [patent_app_country] => US [patent_app_date] => 2021-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12999 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17170616 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/170616
Apparatuses, systems, and methods for analog accumulator for determining row access rate and target row address used for refresh operation Feb 7, 2021 Issued
Array ( [id] => 18073510 [patent_doc_number] => 11532347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => Performing refresh operations of non-volatile memory to mitigate read disturb [patent_app_type] => utility [patent_app_number] => 17/167922 [patent_app_country] => US [patent_app_date] => 2021-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6707 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17167922 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/167922
Performing refresh operations of non-volatile memory to mitigate read disturb Feb 3, 2021 Issued
Array ( [id] => 16995164 [patent_doc_number] => 20210233584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => DIRTY WRITE ON POWER OFF [patent_app_type] => utility [patent_app_number] => 17/165555 [patent_app_country] => US [patent_app_date] => 2021-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14215 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17165555 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/165555
Mitigation of voltage threshold drift associated with power down condition of non-volatile memory device Feb 1, 2021 Issued
Array ( [id] => 16858107 [patent_doc_number] => 20210158852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => ARITHMETIC DEVICES CONDUCTING AUTO-LOAD OPERATION [patent_app_type] => utility [patent_app_number] => 17/164445 [patent_app_country] => US [patent_app_date] => 2021-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15806 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17164445 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/164445
Arithmetic devices conducting auto-load operation for writing the activation functions Jan 31, 2021 Issued
Array ( [id] => 18120347 [patent_doc_number] => 11551745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Computation in-memory architecture for analog-to-digital conversion [patent_app_type] => utility [patent_app_number] => 17/162842 [patent_app_country] => US [patent_app_date] => 2021-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 15237 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17162842 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/162842
Computation in-memory architecture for analog-to-digital conversion Jan 28, 2021 Issued
Array ( [id] => 18219328 [patent_doc_number] => 11594274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Processing in memory (PIM)capable memory device having timing circuity to control timing of operations [patent_app_type] => utility [patent_app_number] => 17/157447 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13831 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17157447 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/157447
Processing in memory (PIM)capable memory device having timing circuity to control timing of operations Jan 24, 2021 Issued
Array ( [id] => 17752469 [patent_doc_number] => 20220230674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => READ OPERATION METHOD FOR NON-VOLATILE MEMORY DEVICE TO REDUCE DISTURBANCE [patent_app_type] => utility [patent_app_number] => 17/153937 [patent_app_country] => US [patent_app_date] => 2021-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4596 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17153937 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/153937
READ OPERATION METHOD FOR NON-VOLATILE MEMORY DEVICE TO REDUCE DISTURBANCE Jan 20, 2021 Abandoned
Array ( [id] => 17543884 [patent_doc_number] => 11309016 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-19 [patent_title] => Variable-latency device to reduce sense error in multi-level multi-bit sensing scheme [patent_app_type] => utility [patent_app_number] => 17/152919 [patent_app_country] => US [patent_app_date] => 2021-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6045 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17152919 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/152919
Variable-latency device to reduce sense error in multi-level multi-bit sensing scheme Jan 19, 2021 Issued
Array ( [id] => 17338521 [patent_doc_number] => 20220004852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => APPARATUS WITH IN-MEMORY PROCESSING AND COMPUTING APPARATUS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/150891 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17150891 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/150891
Apparatus and method with in-memory delay dependent processing Jan 14, 2021 Issued
Array ( [id] => 17402634 [patent_doc_number] => 20220044725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => STACKED MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/150854 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6176 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17150854 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/150854
Stacked DRAM memory device for improving integration density and reducing bit line capacitance Jan 14, 2021 Issued
Array ( [id] => 17716388 [patent_doc_number] => 11380386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Nonvolatile memory device including sensing time control circuit and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/147557 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 28 [patent_no_of_words] => 18295 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17147557 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/147557
Nonvolatile memory device including sensing time control circuit and operating method thereof Jan 12, 2021 Issued
Array ( [id] => 17737735 [patent_doc_number] => 20220223197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => MEMORY UNIT WITH ASYMMETRIC GROUP-MODULATED INPUT SCHEME AND CURRENT-TO-VOLTAGE SIGNAL STACKING SCHEME FOR NON-VOLATILE COMPUTING-IN-MEMORY APPLICATIONS AND COMPUTING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/148504 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6474 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17148504 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/148504
Memory unit with asymmetric group-modulated input scheme and current-to-voltage signal stacking scheme for non-volatile computing-in-memory applications and computing method thereof Jan 12, 2021 Issued
Array ( [id] => 17971131 [patent_doc_number] => 11488678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Grouping flash storage blocks based on robustness for cache program operations and regular program operations [patent_app_type] => utility [patent_app_number] => 17/147539 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4984 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17147539 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/147539
Grouping flash storage blocks based on robustness for cache program operations and regular program operations Jan 12, 2021 Issued
Menu