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Mushfique Siddique

Examiner (ID: 16359, Phone: (571)270-0424 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
838
Issued Applications
687
Pending Applications
93
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17622971 [patent_doc_number] => 11342030 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-24 [patent_title] => Erase voltage compensation mechanism for group erase mode with bit line leakage detection method [patent_app_type] => utility [patent_app_number] => 17/145415 [patent_app_country] => US [patent_app_date] => 2021-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2981 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17145415 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/145415
Erase voltage compensation mechanism for group erase mode with bit line leakage detection method Jan 10, 2021 Issued
Array ( [id] => 17737734 [patent_doc_number] => 20220223196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => INTEGRATED ASSEMBLY WITH MEMORY ARRAY OVER BASE, SENSE AMPLIFIERS IN BASE, AND VERTICALLY-EXTENDING DIGIT LINES ASSOCIATED WITH THE MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 17/146223 [patent_app_country] => US [patent_app_date] => 2021-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17146223 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/146223
Integrated assembly with memory array over base, sense amplifiers in base, and vertically-extending digit lines associated with the memory array Jan 10, 2021 Issued
Array ( [id] => 17737729 [patent_doc_number] => 20220223191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-14 [patent_title] => INTEGRATED ASSEMBLIES HAVING MEMORY CELLS WITH CAPACITIVE UNITS AND REFERENCE-VOLTAGE-GENERATORS WITH RESISTIVE UNITS [patent_app_type] => utility [patent_app_number] => 17/144461 [patent_app_country] => US [patent_app_date] => 2021-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6035 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17144461 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/144461
Integrated assemblies having memory cells with capacitive units and reference-voltage-generators with resistive units Jan 7, 2021 Issued
Array ( [id] => 19231180 [patent_doc_number] => 12010831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => 3D DRAM with multiple memory tiers and vertically extending digit lines [patent_app_type] => utility [patent_app_number] => 17/141426 [patent_app_country] => US [patent_app_date] => 2021-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5622 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17141426 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/141426
3D DRAM with multiple memory tiers and vertically extending digit lines Jan 4, 2021 Issued
Array ( [id] => 17338529 [patent_doc_number] => 20220004860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => ADAPTIVE BIAS DECODER FOR ANALOG NEURAL MEMORY ARRAY IN ARTIFICIAL NEURAL NETWORK [patent_app_type] => utility [patent_app_number] => 17/140924 [patent_app_country] => US [patent_app_date] => 2021-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -43 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17140924 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/140924
Adaptive bias decoder to provide a voltage to a control gate line in an analog neural memory array in artificial neural network Jan 3, 2021 Issued
Array ( [id] => 17668112 [patent_doc_number] => 11361815 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-06-14 [patent_title] => Method and memory device including plurality of memory banks and having shared delay circuit [patent_app_type] => utility [patent_app_number] => 17/134126 [patent_app_country] => US [patent_app_date] => 2020-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5591 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134126 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/134126
Method and memory device including plurality of memory banks and having shared delay circuit Dec 23, 2020 Issued
Array ( [id] => 19487094 [patent_doc_number] => 12106818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-01 [patent_title] => Power control of a memory device in connected standby state [patent_app_type] => utility [patent_app_number] => 17/133484 [patent_app_country] => US [patent_app_date] => 2020-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7704 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17133484 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/133484
Power control of a memory device in connected standby state Dec 22, 2020 Issued
Array ( [id] => 17803073 [patent_doc_number] => 11417382 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-16 [patent_title] => Apparatuses and methods for skipping wordline activation of defective memory during refresh operations [patent_app_type] => utility [patent_app_number] => 17/125051 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6111 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17125051 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/125051
Apparatuses and methods for skipping wordline activation of defective memory during refresh operations Dec 16, 2020 Issued
Array ( [id] => 16811794 [patent_doc_number] => 20210134349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => ARITHMETIC DEVICES CONDUCTING AUTO-LOAD OPERATION [patent_app_type] => utility [patent_app_number] => 17/125671 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15655 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17125671 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/125671
Arithmetic devices conducting auto-load operation for writing the activation functions Dec 16, 2020 Issued
Array ( [id] => 17978437 [patent_doc_number] => 11495309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Initiating media management operation using voltage distribution metrics in memory system [patent_app_type] => utility [patent_app_number] => 17/123997 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11592 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17123997 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/123997
Initiating media management operation using voltage distribution metrics in memory system Dec 15, 2020 Issued
Array ( [id] => 16730888 [patent_doc_number] => 20210098036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/119821 [patent_app_country] => US [patent_app_date] => 2020-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10330 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17119821 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/119821
Resistive memory device for lowering resistance value of memory cell during set program operation Dec 10, 2020 Issued
Array ( [id] => 18137091 [patent_doc_number] => 11562779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Bit line secondary drive circuit and method [patent_app_type] => utility [patent_app_number] => 17/109964 [patent_app_country] => US [patent_app_date] => 2020-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 11962 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17109964 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/109964
Bit line secondary drive circuit and method Dec 1, 2020 Issued
Array ( [id] => 16715377 [patent_doc_number] => 20210082524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/104564 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19262 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17104564 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/104564
Information processing system including host device and memory system Nov 24, 2020 Issued
Array ( [id] => 16752261 [patent_doc_number] => 20210104273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => CLOCK SIGNAL GENERATOR GENERATING FOUR-PHASE CLOCK SIGNALS [patent_app_type] => utility [patent_app_number] => 17/104909 [patent_app_country] => US [patent_app_date] => 2020-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4787 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17104909 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/104909
Clock signal generator generating four-phase clock signals Nov 24, 2020 Issued
Array ( [id] => 18120348 [patent_doc_number] => 11551746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Apparatuses including memory regions having different access speeds and methods for using the same [patent_app_type] => utility [patent_app_number] => 16/953214 [patent_app_country] => US [patent_app_date] => 2020-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8543 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16953214 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/953214
Apparatuses including memory regions having different access speeds and methods for using the same Nov 18, 2020 Issued
Array ( [id] => 18967209 [patent_doc_number] => 11900987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Non-volatile static random access memory with independently accessible non-volatile bit cell and method of operating the same [patent_app_type] => utility [patent_app_number] => 16/951919 [patent_app_country] => US [patent_app_date] => 2020-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4311 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16951919 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/951919
Non-volatile static random access memory with independently accessible non-volatile bit cell and method of operating the same Nov 17, 2020 Issued
Array ( [id] => 17615088 [patent_doc_number] => 20220157368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => VOLTAGE DROP MITIGATION TECHNIQUES FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/950593 [patent_app_country] => US [patent_app_date] => 2020-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10280 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16950593 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/950593
Voltage drop mitigation techniques for memory devices Nov 16, 2020 Issued
Array ( [id] => 17516672 [patent_doc_number] => 11295832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Plate defect mitigation techniques [patent_app_type] => utility [patent_app_number] => 16/950613 [patent_app_country] => US [patent_app_date] => 2020-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 29118 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16950613 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/950613
Plate defect mitigation techniques Nov 16, 2020 Issued
Array ( [id] => 17318524 [patent_doc_number] => 20210407574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => SEMICONDUCTOR MEMORY DEVICE INCLUDING LATENCY SETTING CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/097151 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14104 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17097151 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/097151
Semiconductor memory device capable of operating at high speed, low power environment by optimizing latency of read command and write command depending on various operation modes Nov 12, 2020 Issued
Array ( [id] => 17599068 [patent_doc_number] => 20220148642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => WORD LINES COUPLED TO PULL-DOWN TRANSISTORS, AND RELATED DEVICES, SYSTEMS, AND METHODS [patent_app_type] => utility [patent_app_number] => 17/096476 [patent_app_country] => US [patent_app_date] => 2020-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6250 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17096476 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/096476
Word lines coupled to pull-down transistors, and related devices, systems, and methods Nov 11, 2020 Issued
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