| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 17925677
[patent_doc_number] => 11468936
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-10-11
[patent_title] => Semiconductor memory device capable of performing target refresh operation on active command basis and refresh command basis, and operating method thereof
[patent_app_type] => utility
[patent_app_number] => 17/095494
[patent_app_country] => US
[patent_app_date] => 2020-11-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6911
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17095494
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/095494 | Semiconductor memory device capable of performing target refresh operation on active command basis and refresh command basis, and operating method thereof | Nov 10, 2020 | Issued |
Array
(
[id] => 16631384
[patent_doc_number] => 20210050037
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-18
[patent_title] => NONVOLATILE MEMORY APPARATUS, AND READ AND WRITE METHOD OF THE NONVOLATILE MEMORY APPARATUS
[patent_app_type] => utility
[patent_app_number] => 17/089364
[patent_app_country] => US
[patent_app_date] => 2020-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9192
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17089364
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/089364 | NONVOLATILE MEMORY APPARATUS, AND READ AND WRITE METHOD OF THE NONVOLATILE MEMORY APPARATUS | Nov 3, 2020 | Abandoned |
Array
(
[id] => 16850362
[patent_doc_number] => 20210151107
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-05-20
[patent_title] => MEMORY CELL SELECTION
[patent_app_type] => utility
[patent_app_number] => 17/089146
[patent_app_country] => US
[patent_app_date] => 2020-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14606
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17089146
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/089146 | Techniques for applying multiple voltage pulses to select a memory cell | Nov 3, 2020 | Issued |
Array
(
[id] => 16660380
[patent_doc_number] => 20210057017
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-25
[patent_title] => WORDLINE DRIVING CIRCUIT AND MEMORY CELL
[patent_app_type] => utility
[patent_app_number] => 17/086476
[patent_app_country] => US
[patent_app_date] => 2020-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3648
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17086476
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/086476 | WORDLINE DRIVING CIRCUIT AND MEMORY CELL | Nov 1, 2020 | Abandoned |
Array
(
[id] => 17566298
[patent_doc_number] => 20220130447
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-28
[patent_title] => MEMORY DEVICE ARCHITECTURE USING MULTIPLE CELLS PER BIT
[patent_app_type] => utility
[patent_app_number] => 17/080310
[patent_app_country] => US
[patent_app_date] => 2020-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7208
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17080310
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/080310 | Memory device architecture using multiple physical cells per bit to improve read margin and to alleviate the need for managing demarcation read voltages | Oct 25, 2020 | Issued |
Array
(
[id] => 16858112
[patent_doc_number] => 20210158857
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-05-27
[patent_title] => IN-MEMORY COMPUTING DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/077795
[patent_app_country] => US
[patent_app_date] => 2020-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2336
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17077795
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/077795 | In-memory multiply-add computing device adapted to process input signals with improved accuracy | Oct 21, 2020 | Issued |
Array
(
[id] => 17410008
[patent_doc_number] => 11250904
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-02-15
[patent_title] => DRAM with inter-section, page-data-copy scheme for low power and wide data access
[patent_app_type] => utility
[patent_app_number] => 17/037755
[patent_app_country] => US
[patent_app_date] => 2020-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 4055
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 277
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17037755
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/037755 | DRAM with inter-section, page-data-copy scheme for low power and wide data access | Sep 29, 2020 | Issued |
Array
(
[id] => 17246788
[patent_doc_number] => 20210366533
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-25
[patent_title] => VOLTAGE SUPPLY CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/039118
[patent_app_country] => US
[patent_app_date] => 2020-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9282
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17039118
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/039118 | Voltage supply circuit for supplying a driving voltage to a sense amplifying circuit of a semiconductor memory device | Sep 29, 2020 | Issued |
Array
(
[id] => 16981185
[patent_doc_number] => 20210225422
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-07-22
[patent_title] => VOLTAGE GENERATOR CIRCUITRY OF MEMORY DEVICE AND METHODS OF OPERATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/034058
[patent_app_country] => US
[patent_app_date] => 2020-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9340
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17034058
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/034058 | Voltage generator circuitry of memory device for generating an internal power supply voltage and methods of operating the same | Sep 27, 2020 | Issued |
Array
(
[id] => 16578454
[patent_doc_number] => 20210012855
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-01-14
[patent_title] => Method and Apparatus for enabling Multiple Return Material Authorizations (RMAs) on an Integrated Circuit Device
[patent_app_type] => utility
[patent_app_number] => 17/033526
[patent_app_country] => US
[patent_app_date] => 2020-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5651
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17033526
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/033526 | Method and apparatus for enabling multiple return material authorizations (RMAs) on an integrated circuit device | Sep 24, 2020 | Issued |
Array
(
[id] => 17485654
[patent_doc_number] => 20220093158
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-24
[patent_title] => MEMORY SUBWORD DRIVER CIRCUITS AND LAYOUT
[patent_app_type] => utility
[patent_app_number] => 17/028929
[patent_app_country] => US
[patent_app_date] => 2020-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11921
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17028929
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/028929 | Semiconductor memory subword driver circuits and layout | Sep 21, 2020 | Issued |
Array
(
[id] => 16896535
[patent_doc_number] => 11038098
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-15
[patent_title] => Magnetic random access memory with various size magnetic tunneling junction film stacks
[patent_app_type] => utility
[patent_app_number] => 17/027379
[patent_app_country] => US
[patent_app_date] => 2020-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 35
[patent_no_of_words] => 9979
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17027379
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/027379 | Magnetic random access memory with various size magnetic tunneling junction film stacks | Sep 20, 2020 | Issued |
Array
(
[id] => 16544665
[patent_doc_number] => 20200411080
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-31
[patent_title] => VOLATILE MEMORY DEVICE WITH 3-D STRUCTURE INCLUDING VERTICAL PILLARS AND MEMORY CELLS VERTICALLY STACKED ONE OVER ANOTHER IN MULTIPLE LEVELS
[patent_app_type] => utility
[patent_app_number] => 17/020536
[patent_app_country] => US
[patent_app_date] => 2020-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 24100
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17020536
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/020536 | Volatile memory device with 3-D structure including memory cells having transistors vertically stacked one over another | Sep 13, 2020 | Issued |
Array
(
[id] => 16920121
[patent_doc_number] => 20210193213
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-24
[patent_title] => MEMORY DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/016481
[patent_app_country] => US
[patent_app_date] => 2020-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9605
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17016481
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/016481 | Memory devices configured to detect internal potential failures | Sep 9, 2020 | Issued |
Array
(
[id] => 17137453
[patent_doc_number] => 11139018
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-10-05
[patent_title] => Memory device with temporary kickdown of source voltage before sensing
[patent_app_type] => utility
[patent_app_number] => 17/007442
[patent_app_country] => US
[patent_app_date] => 2020-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 17
[patent_no_of_words] => 14619
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17007442
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/007442 | Memory device with temporary kickdown of source voltage before sensing | Aug 30, 2020 | Issued |
Array
(
[id] => 17716386
[patent_doc_number] => 11380384
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-05
[patent_title] => Buried power rail structure for providing multi-domain power supply for memory device
[patent_app_type] => utility
[patent_app_number] => 17/006689
[patent_app_country] => US
[patent_app_date] => 2020-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5507
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17006689
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/006689 | Buried power rail structure for providing multi-domain power supply for memory device | Aug 27, 2020 | Issued |
Array
(
[id] => 17878354
[patent_doc_number] => 11450375
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-09-20
[patent_title] => Semiconductor memory devices including subword driver and layouts thereof
[patent_app_type] => utility
[patent_app_number] => 17/006730
[patent_app_country] => US
[patent_app_date] => 2020-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 12141
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17006730
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/006730 | Semiconductor memory devices including subword driver and layouts thereof | Aug 27, 2020 | Issued |
Array
(
[id] => 17971108
[patent_doc_number] => 11488655
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-01
[patent_title] => Subword drivers with reduced numbers of transistors and circuit layout of the same
[patent_app_type] => utility
[patent_app_number] => 17/006722
[patent_app_country] => US
[patent_app_date] => 2020-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 12141
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 254
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17006722
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/006722 | Subword drivers with reduced numbers of transistors and circuit layout of the same | Aug 27, 2020 | Issued |
Array
(
[id] => 18235783
[patent_doc_number] => 11600347
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-03-07
[patent_title] => Storage device
[patent_app_type] => utility
[patent_app_number] => 17/004823
[patent_app_country] => US
[patent_app_date] => 2020-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 7224
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17004823
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/004823 | Storage device | Aug 26, 2020 | Issued |
Array
(
[id] => 17878352
[patent_doc_number] => 11450373
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-09-20
[patent_title] => Memory system capable of compensating for kickback noise
[patent_app_type] => utility
[patent_app_number] => 17/003163
[patent_app_country] => US
[patent_app_date] => 2020-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 14238
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17003163
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/003163 | Memory system capable of compensating for kickback noise | Aug 25, 2020 | Issued |