Search

Mushfique Siddique

Examiner (ID: 16359, Phone: (571)270-0424 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
838
Issued Applications
687
Pending Applications
93
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17971107 [patent_doc_number] => 11488654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Memory row recording for mitigating crosstalk in dynamic random access memory [patent_app_type] => utility [patent_app_number] => 16/902204 [patent_app_country] => US [patent_app_date] => 2020-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5913 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16902204 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/902204
Memory row recording for mitigating crosstalk in dynamic random access memory Jun 14, 2020 Issued
Array ( [id] => 19982102 [patent_doc_number] => 12349605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Method for manufacturing an OxRAM type resistive memory cell [patent_app_type] => utility [patent_app_number] => 17/618295 [patent_app_country] => US [patent_app_date] => 2020-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1898 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17618295 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/618295
Method for manufacturing an OxRAM type resistive memory cell Jun 10, 2020 Issued
Array ( [id] => 17558918 [patent_doc_number] => 11315637 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-26 [patent_title] => Adaptive erase voltage based on temperature [patent_app_type] => utility [patent_app_number] => 16/891702 [patent_app_country] => US [patent_app_date] => 2020-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 9706 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16891702 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/891702
Adaptive erase voltage based on temperature Jun 2, 2020 Issued
Array ( [id] => 17195855 [patent_doc_number] => 11164620 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-02 [patent_title] => Timing signal calibration for access operation of a memory device [patent_app_type] => utility [patent_app_number] => 16/891601 [patent_app_country] => US [patent_app_date] => 2020-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 14913 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16891601 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/891601
Timing signal calibration for access operation of a memory device Jun 2, 2020 Issued
Array ( [id] => 17262368 [patent_doc_number] => 20210375353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => PERFORMING IN-MEMORY COMPUTING BASED ON MULTIPLY-ACCUMULATE OPERATIONS USING NON-VOLATILE MEMORY ARRAYS [patent_app_type] => utility [patent_app_number] => 16/886995 [patent_app_country] => US [patent_app_date] => 2020-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3181 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16886995 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/886995
Performing in-memory computing based on multiply-accumulate operations using non-volatile memory arrays May 28, 2020 Issued
Array ( [id] => 18054144 [patent_doc_number] => 11527539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-13 [patent_title] => Four-poly-pitch SRAM cell with backside metal tracks [patent_app_type] => utility [patent_app_number] => 16/888269 [patent_app_country] => US [patent_app_date] => 2020-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8321 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16888269 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/888269
Four-poly-pitch SRAM cell with backside metal tracks May 28, 2020 Issued
Array ( [id] => 17165963 [patent_doc_number] => 11152071 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-10-19 [patent_title] => Erase operation reattempt to recover misidentified bad blocks resulting from consecutive erase failures [patent_app_type] => utility [patent_app_number] => 16/885147 [patent_app_country] => US [patent_app_date] => 2020-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9640 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16885147 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/885147
Erase operation reattempt to recover misidentified bad blocks resulting from consecutive erase failures May 26, 2020 Issued
Array ( [id] => 16585855 [patent_doc_number] => 20210020257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => SEMICONDUCTOR DEVICE AND SENSOR APPARATUS [patent_app_type] => utility [patent_app_number] => 16/882531 [patent_app_country] => US [patent_app_date] => 2020-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7639 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16882531 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/882531
Semiconductor device with a diagnosing section that diagnoses correction memory and sensor apparatus May 23, 2020 Issued
Array ( [id] => 16920122 [patent_doc_number] => 20210193214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/878128 [patent_app_country] => US [patent_app_date] => 2020-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11193 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16878128 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/878128
SEMICONDUCTOR DEVICES May 18, 2020 Abandoned
Array ( [id] => 17253840 [patent_doc_number] => 11189336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Word line driving device for minimizing RC delay [patent_app_type] => utility [patent_app_number] => 16/878594 [patent_app_country] => US [patent_app_date] => 2020-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6580 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16878594 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/878594
Word line driving device for minimizing RC delay May 18, 2020 Issued
Array ( [id] => 17224483 [patent_doc_number] => 11176993 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-16 [patent_title] => Synapse element increasing a dynamic range of an output while suppressing and/or decreasing power consumption, and a neuromorphic processor including the synapse element [patent_app_type] => utility [patent_app_number] => 16/876563 [patent_app_country] => US [patent_app_date] => 2020-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11189 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16876563 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/876563
Synapse element increasing a dynamic range of an output while suppressing and/or decreasing power consumption, and a neuromorphic processor including the synapse element May 17, 2020 Issued
Array ( [id] => 18396793 [patent_doc_number] => 20230165014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => TWO-DIMENSIONAL MATERIAL-BASED SELECTOR, MEMORY UNIT, ARRAY, AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/998782 [patent_app_country] => US [patent_app_date] => 2020-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11754 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17998782 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/998782
Two-dimensional material-based selector with stack unit, memory unit, array, and method of operating the same May 14, 2020 Issued
Array ( [id] => 18396793 [patent_doc_number] => 20230165014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => TWO-DIMENSIONAL MATERIAL-BASED SELECTOR, MEMORY UNIT, ARRAY, AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/998782 [patent_app_country] => US [patent_app_date] => 2020-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11754 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17998782 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/998782
Two-dimensional material-based selector with stack unit, memory unit, array, and method of operating the same May 14, 2020 Issued
Array ( [id] => 18704451 [patent_doc_number] => 11790967 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Magnetic domain wall displacement element, magnetic recording array, and semiconductor device [patent_app_type] => utility [patent_app_number] => 17/420053 [patent_app_country] => US [patent_app_date] => 2020-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 13780 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17420053 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/420053
Magnetic domain wall displacement element, magnetic recording array, and semiconductor device May 14, 2020 Issued
Array ( [id] => 16973417 [patent_doc_number] => 11069396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-20 [patent_title] => Memory device and method of operating the memory device for initializing sensing latch during evaluation operation [patent_app_type] => utility [patent_app_number] => 16/874236 [patent_app_country] => US [patent_app_date] => 2020-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11655 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16874236 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/874236
Memory device and method of operating the memory device for initializing sensing latch during evaluation operation May 13, 2020 Issued
Array ( [id] => 17032555 [patent_doc_number] => 11094372 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-17 [patent_title] => Partial writing method of dram memoryl device to reduce power consumption associated with large voltage swing of internal input/output lines [patent_app_type] => utility [patent_app_number] => 16/868544 [patent_app_country] => US [patent_app_date] => 2020-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7591 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16868544 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/868544
Partial writing method of dram memoryl device to reduce power consumption associated with large voltage swing of internal input/output lines May 6, 2020 Issued
Array ( [id] => 17137465 [patent_doc_number] => 11139030 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-10-05 [patent_title] => Reducing post-read disturb in a nonvolatile memory device [patent_app_type] => utility [patent_app_number] => 16/861697 [patent_app_country] => US [patent_app_date] => 2020-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 33 [patent_no_of_words] => 21297 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16861697 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/861697
Reducing post-read disturb in a nonvolatile memory device Apr 28, 2020 Issued
Array ( [id] => 16440143 [patent_doc_number] => 20200357470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => VOLTAGE SUPPLY CIRCUIT, MEMORY CELL ARRANGEMENT, AND METHOD FOR OPERATING A MEMORY CELL ARRANGEMENT [patent_app_type] => utility [patent_app_number] => 16/861611 [patent_app_country] => US [patent_app_date] => 2020-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23911 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16861611 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/861611
Voltage supply circuit, memory cell arrangement, and method for operating a memory cell arrangement Apr 28, 2020 Issued
Array ( [id] => 16943924 [patent_doc_number] => 11056172 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-07-06 [patent_title] => Flash memory and operation method thereof for controlling raising speed of the read pass voltage [patent_app_type] => utility [patent_app_number] => 16/860349 [patent_app_country] => US [patent_app_date] => 2020-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3498 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16860349 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/860349
Flash memory and operation method thereof for controlling raising speed of the read pass voltage Apr 27, 2020 Issued
Array ( [id] => 16624595 [patent_doc_number] => 20210043248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => ROW HAMMER PREVENTION CIRCUIT, A MEMORY MODULE INCLUDING THE ROW HAMMER PREVENTION CIRCUIT, AND A MEMORY SYSTEM INCLUDING THE MEMORY MODULE [patent_app_type] => utility [patent_app_number] => 16/858468 [patent_app_country] => US [patent_app_date] => 2020-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5265 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16858468 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/858468
Row hammer prevention circuit, a memory module including the row hammer prevention circuit, and a memory system including the memory module Apr 23, 2020 Issued
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