Search

Mushfique Siddique

Examiner (ID: 16359, Phone: (571)270-0424 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
838
Issued Applications
687
Pending Applications
93
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16347745 [patent_doc_number] => 20200312396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/814678 [patent_app_country] => US [patent_app_date] => 2020-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7738 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16814678 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/814678
Resistive memory device having read currents for a memory cell and a reference cell in opposite directions Mar 9, 2020 Issued
Array ( [id] => 17047800 [patent_doc_number] => 11100990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Memory device for avoiding multi-turn on of memory cell during reading, and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/813826 [patent_app_country] => US [patent_app_date] => 2020-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 14988 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16813826 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/813826
Memory device for avoiding multi-turn on of memory cell during reading, and operating method thereof Mar 9, 2020 Issued
Array ( [id] => 16660391 [patent_doc_number] => 20210057028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/810910 [patent_app_country] => US [patent_app_date] => 2020-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 631 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16810910 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/810910
Non-volatile semiconductor memory device including a first memory bunch and a second memory bunch Mar 5, 2020 Issued
Array ( [id] => 16616963 [patent_doc_number] => 20210035616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => DATA LINE SWITCHING CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/808228 [patent_app_country] => US [patent_app_date] => 2020-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5149 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16808228 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/808228
Dram data line switching control circuit and minimizing number of data line switches for power reduction Mar 2, 2020 Issued
Array ( [id] => 17032549 [patent_doc_number] => 11094366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Systems and methods to control semiconductor memory device in various timings [patent_app_type] => utility [patent_app_number] => 16/805379 [patent_app_country] => US [patent_app_date] => 2020-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 14552 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 520 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16805379 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/805379
Systems and methods to control semiconductor memory device in various timings Feb 27, 2020 Issued
Array ( [id] => 17018194 [patent_doc_number] => 11087839 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Nonvolatile memory device with vertical string including semiconductor and resistance change layers, and method of operating the same [patent_app_type] => utility [patent_app_number] => 16/802803 [patent_app_country] => US [patent_app_date] => 2020-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9238 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16802803 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/802803
Nonvolatile memory device with vertical string including semiconductor and resistance change layers, and method of operating the same Feb 26, 2020 Issued
Array ( [id] => 16347750 [patent_doc_number] => 20200312401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 16/803964 [patent_app_country] => US [patent_app_date] => 2020-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14061 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16803964 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/803964
Semiconductor storage device for high-speed burst access Feb 26, 2020 Issued
Array ( [id] => 17047785 [patent_doc_number] => 11100975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Semiconductor memory device and method for adjusting threthold voltage thereof [patent_app_type] => utility [patent_app_number] => 16/803260 [patent_app_country] => US [patent_app_date] => 2020-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 12407 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16803260 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/803260
Semiconductor memory device and method for adjusting threthold voltage thereof Feb 26, 2020 Issued
Array ( [id] => 17062931 [patent_doc_number] => 11107540 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-31 [patent_title] => Program disturb improvements in multi-tier memory devices including improved non-data conductive gate implementation [patent_app_type] => utility [patent_app_number] => 16/791253 [patent_app_country] => US [patent_app_date] => 2020-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 10254 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16791253 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/791253
Program disturb improvements in multi-tier memory devices including improved non-data conductive gate implementation Feb 13, 2020 Issued
Array ( [id] => 17018201 [patent_doc_number] => 11087846 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-10 [patent_title] => Memory system with single decoder, multiple memory sets and method for decoding multiple codewords from memory sets using the single decoder [patent_app_type] => utility [patent_app_number] => 16/788989 [patent_app_country] => US [patent_app_date] => 2020-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6705 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16788989 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/788989
Memory system with single decoder, multiple memory sets and method for decoding multiple codewords from memory sets using the single decoder Feb 11, 2020 Issued
Array ( [id] => 16616969 [patent_doc_number] => 20210035622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/787726 [patent_app_country] => US [patent_app_date] => 2020-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11249 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16787726 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/787726
Apparatus and method for non-volatile memory for applying voltages to selected and unselected strings during the channel initialization for improved read operation Feb 10, 2020 Issued
Array ( [id] => 16001607 [patent_doc_number] => 20200176674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => 1S1R MEMORY INTEGRATED STRUCTURE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/786346 [patent_app_country] => US [patent_app_date] => 2020-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3524 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16786346 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/786346
1S1R memory integrated structure with larger selector surface area which can effectively suppress leakage current in the cross array without increasing the overall size of the integrated structure and method for fabricating the same Feb 9, 2020 Issued
Array ( [id] => 16616981 [patent_doc_number] => 20210035634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => RESISITIVE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/786609 [patent_app_country] => US [patent_app_date] => 2020-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10030 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16786609 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/786609
Methods and apparatus for resisitive memory device for sense margin compensation Feb 9, 2020 Issued
Array ( [id] => 16241330 [patent_doc_number] => 20200258564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => DECODER STRUCTURE FOR A MEMORY ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 16/786814 [patent_app_country] => US [patent_app_date] => 2020-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3028 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16786814 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/786814
Decoder structure including array of decoder cells organized into different rows Feb 9, 2020 Issued
Array ( [id] => 17047775 [patent_doc_number] => 11100964 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-08-24 [patent_title] => Multi-stage bit line pre-charge [patent_app_type] => utility [patent_app_number] => 16/785875 [patent_app_country] => US [patent_app_date] => 2020-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4121 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16785875 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/785875
Multi-stage bit line pre-charge Feb 9, 2020 Issued
Array ( [id] => 18169984 [patent_doc_number] => 20230036595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => BLOCK-TO-BLOCK ISOLATION AND DEEP CONTACT USING PILLARS IN A MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 17/791176 [patent_app_country] => US [patent_app_date] => 2020-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17791176 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/791176
Block-to-block isolation and deep contact using pillars in a memory array Feb 7, 2020 Issued
Array ( [id] => 16888655 [patent_doc_number] => 20210174852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => Method of Reducing Program Disturbance in Memory Device and Memory Device Utilizing Same [patent_app_type] => utility [patent_app_number] => 16/740491 [patent_app_country] => US [patent_app_date] => 2020-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4862 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16740491 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/740491
Method of sequentially biasing bias lines in memory device for program disturbance reduction and memory device utilizing same Jan 12, 2020 Issued
Array ( [id] => 16943950 [patent_doc_number] => 11056198 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-06 [patent_title] => Read disturb scan consolidation [patent_app_type] => utility [patent_app_number] => 16/741198 [patent_app_country] => US [patent_app_date] => 2020-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8259 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16741198 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/741198
Read disturb scan consolidation Jan 12, 2020 Issued
Array ( [id] => 16936096 [patent_doc_number] => 20210201985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => METHOD FOR REFRESHING MEMORY DEVICE WHERE CONTROL CIRCUIT PERFORMS FIRST REFRESH OPERATION ON FIRST GROUP AND PERFORMS SECOND REFRESH OPERATION ON VICTIM ROW OF SECOND GROUP WITHOUT EXTERNAL COMMAND FOR VICTIM ROW REFRESH [patent_app_type] => utility [patent_app_number] => 16/731081 [patent_app_country] => US [patent_app_date] => 2019-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16731081 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/731081
Method for refreshing a memory device, in which the victim row refresh operation is hidden in the normal refresh operation without affecting the time allocated for the normal refresh operation Dec 30, 2019 Issued
Array ( [id] => 17062921 [patent_doc_number] => 11107530 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-31 [patent_title] => Non-volatile static random access memory (nvSRAM) with multiple magnetic tunnel junction cells [patent_app_type] => utility [patent_app_number] => 16/732219 [patent_app_country] => US [patent_app_date] => 2019-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9900 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16732219 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/732219
Non-volatile static random access memory (nvSRAM) with multiple magnetic tunnel junction cells Dec 30, 2019 Issued
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