Mushfique Siddique

Array ( [id] => 16958903 [patent_doc_number] => 11062780 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-07-13 [patent_title] => System and method of reading two pages in a nonvolatile memory [patent_app_type] => utility [patent_app_number] => 16/729951 [patent_app_country] => US [patent_app_date] => 2019-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8383 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16729951 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19678127 [patent_doc_number] => 12189988 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Write broadcast operations associated with a memory device [patent_app_type] => utility [patent_app_number] => 17/414298 [patent_app_country] => US [patent_app_date] => 2019-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 44309 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17414298 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16515804 [patent_doc_number] => 20200395062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => SEMICONDUCTOR MEMORY DEVICE INCLUDING A CONTROL CIRCUIT FOR CONTROLLING A READ OPERATION [patent_app_type] => utility [patent_app_number] => 16/712737 [patent_app_country] => US [patent_app_date] => 2019-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6144 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16712737 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16684173 [patent_doc_number] => 10943662 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-09 [patent_title] => Different word line programming orders in non-volatile memory for error recovery [patent_app_type] => utility [patent_app_number] => 16/709709 [patent_app_country] => US [patent_app_date] => 2019-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 37 [patent_no_of_words] => 25587 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16709709 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16021097 [patent_doc_number] => 20200185392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-11 [patent_title] => 3D INTEGRATED CIRCUIT RANDOM-ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 16/708623 [patent_app_country] => US [patent_app_date] => 2019-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6489 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16708623 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16887697 [patent_doc_number] => 20210173894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => ARRAY OF INTEGRATED PIXEL AND MEMORY CELLS FOR DEEP IN-SENSOR, IN-MEMORY COMPUTING [patent_app_type] => utility [patent_app_number] => 16/705434 [patent_app_country] => US [patent_app_date] => 2019-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9018 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16705434 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16880900 [patent_doc_number] => 11031056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Clock generation circuitry for memory device to generate multi-phase clocks and output data clocks to sort and serialize output data [patent_app_type] => utility [patent_app_number] => 16/706349 [patent_app_country] => US [patent_app_date] => 2019-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5451 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16706349 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16759556 [patent_doc_number] => 10978111 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-13 [patent_title] => Sense amplifier circuit with reference voltage holding circuit for maintaining sense amplifier reference voltage when the sense amplifier operates under standby mode [patent_app_type] => utility [patent_app_number] => 16/705147 [patent_app_country] => US [patent_app_date] => 2019-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3968 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16705147 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16811815 [patent_doc_number] => 20210134370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => METHOD OF CONCURRENT MULTI-STATE PROGRAMMING OF NON-VOLATILE MEMORY WITH BIT LINE VOLTAGE STEP UP [patent_app_type] => utility [patent_app_number] => 16/701450 [patent_app_country] => US [patent_app_date] => 2019-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16701450 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17318529 [patent_doc_number] => 20210407579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => DRAM DEVICE WITH MULTIPLE VOLTAGE DOMAINS [patent_app_type] => utility [patent_app_number] => 17/295753 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4470 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17295753 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18016153 [patent_doc_number] => 11508456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Semiconductor memory device capable of increasing flexibility of a column repair operation [patent_app_type] => utility [patent_app_number] => 16/685458 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 32 [patent_no_of_words] => 12331 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 386 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16685458 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15656417 [patent_doc_number] => 20200090739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => Quantum Metrology and Quantum Memory Using Defect Sates with Spin -3/2 or Higher Half-Spin Multiplets [patent_app_type] => utility [patent_app_number] => 16/684707 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11235 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16684707 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16279916 [patent_doc_number] => 10762954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Quantum metrology and quantum memory using defect sates with spin-3/2 or higher half-spin multiplets [patent_app_type] => utility [patent_app_number] => 16/684673 [patent_app_country] => US [patent_app_date] => 2019-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 11171 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16684673 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16803102 [patent_doc_number] => 10998053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Memory device and operating method thereof for applying a channel precharge voltage to bit lines after a sensing operation [patent_app_type] => utility [patent_app_number] => 16/676157 [patent_app_country] => US [patent_app_date] => 2019-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 18409 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16676157 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16811806 [patent_doc_number] => 20210134361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => PHASE CHANGE ELEMENT CONFIGURED TO INCREASE DISCRETE DATA STATES [patent_app_type] => utility [patent_app_number] => 16/671371 [patent_app_country] => US [patent_app_date] => 2019-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16671371 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16811806 [patent_doc_number] => 20210134361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => PHASE CHANGE ELEMENT CONFIGURED TO INCREASE DISCRETE DATA STATES [patent_app_type] => utility [patent_app_number] => 16/671371 [patent_app_country] => US [patent_app_date] => 2019-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16671371 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16865599 [patent_doc_number] => 11024350 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Semiconductor device including a calibration circuit capable of generating strobe signals and clock signals having accurate duty ratio and training method thereof [patent_app_type] => utility [patent_app_number] => 16/670719 [patent_app_country] => US [patent_app_date] => 2019-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 13632 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16670719 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16811814 [patent_doc_number] => 20210134369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => METHOD FOR CONCURRENT PROGRAMMING [patent_app_type] => utility [patent_app_number] => 16/668675 [patent_app_country] => US [patent_app_date] => 2019-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16668675 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16424811 [patent_doc_number] => 20200350009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-05 [patent_title] => ELECTRONIC DEVICE AND METHOD OF OPERATING THE ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/669245 [patent_app_country] => US [patent_app_date] => 2019-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11602 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16669245 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17277995 [patent_doc_number] => 20210384193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/289357 [patent_app_country] => US [patent_app_date] => 2019-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 62770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17289357 [rel_patent_id] =>[rel_patent_doc_number] =>)