Search

Mushfique Siddique

Examiner (ID: 16359, Phone: (571)270-0424 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
838
Issued Applications
687
Pending Applications
93
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16566630 [patent_doc_number] => 10892004 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-12 [patent_title] => Sub word line driver of semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/657761 [patent_app_country] => US [patent_app_date] => 2019-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6708 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16657761 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/657761
Sub word line driver of semiconductor memory device Oct 17, 2019 Issued
Array ( [id] => 17622958 [patent_doc_number] => 11342017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Key-based multi-qubit memory [patent_app_type] => utility [patent_app_number] => 16/655675 [patent_app_country] => US [patent_app_date] => 2019-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 6204 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16655675 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/655675
Key-based multi-qubit memory Oct 16, 2019 Issued
Array ( [id] => 15839921 [patent_doc_number] => 20200135243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-30 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING SENSE AMPLIFIER AND LATCH [patent_app_type] => utility [patent_app_number] => 16/598795 [patent_app_country] => US [patent_app_date] => 2019-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3802 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16598795 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/598795
Sense amplifier based flip-flop capable of resolving metastable state by removing unintentional current from output nodes Oct 9, 2019 Issued
Array ( [id] => 15746035 [patent_doc_number] => 20200111907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-09 [patent_title] => DEVICES INCLUDING VERTICAL TRANSISTORS, AND RELATED METHODS AND ELECTRONIC SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/596407 [patent_app_country] => US [patent_app_date] => 2019-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6299 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16596407 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/596407
Device including a vertical transistor having a large band gap channel material and void spaces adjacent gate electrodes, and related methods and systems Oct 7, 2019 Issued
Array ( [id] => 16255585 [patent_doc_number] => 20200264959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => STORAGE DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/589900 [patent_app_country] => US [patent_app_date] => 2019-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22080 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16589900 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/589900
STORAGE DEVICE AND METHOD OF OPERATING THE SAME Sep 30, 2019 Abandoned
Array ( [id] => 16746244 [patent_doc_number] => 10971245 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-06 [patent_title] => Measurement of MTJ in a compact memory array [patent_app_type] => utility [patent_app_number] => 16/577839 [patent_app_country] => US [patent_app_date] => 2019-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6091 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16577839 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/577839
Measurement of MTJ in a compact memory array Sep 19, 2019 Issued
Array ( [id] => 16536694 [patent_doc_number] => 10879308 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-29 [patent_title] => Stacked nanosheet 4T2R unit cell for neuromorphic computing [patent_app_type] => utility [patent_app_number] => 16/576551 [patent_app_country] => US [patent_app_date] => 2019-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6940 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16576551 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/576551
Stacked nanosheet 4T2R unit cell for neuromorphic computing Sep 18, 2019 Issued
Array ( [id] => 16951452 [patent_doc_number] => 20210210144 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2021-07-08 [patent_title] => Programming Circuit and Method For Flash Memory Array [patent_app_type] => utility [patent_app_number] => 16/574059 [patent_app_country] => US [patent_app_date] => 2019-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2476 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16574059 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/574059
Programming circuit and method for flash memory array Sep 16, 2019 Issued
Array ( [id] => 16951452 [patent_doc_number] => 20210210144 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2021-07-08 [patent_title] => Programming Circuit and Method For Flash Memory Array [patent_app_type] => utility [patent_app_number] => 16/574059 [patent_app_country] => US [patent_app_date] => 2019-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2476 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16574059 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/574059
Programming circuit and method for flash memory array Sep 16, 2019 Issued
Array ( [id] => 15624925 [patent_doc_number] => 20200082867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => MEMORY CELL IN CAPACITIVE LOGIC [patent_app_type] => utility [patent_app_number] => 16/567927 [patent_app_country] => US [patent_app_date] => 2019-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16567927 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/567927
Memory cells with capacitive logic based on electromechanically controlled variable-capacitance capacitors Sep 10, 2019 Issued
Array ( [id] => 16347744 [patent_doc_number] => 20200312395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-01 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/567901 [patent_app_country] => US [patent_app_date] => 2019-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16567901 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/567901
Semiconductor memory device Sep 10, 2019 Issued
Array ( [id] => 16332027 [patent_doc_number] => 20200302993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => SEMICONDUCTOR MEMORY [patent_app_type] => utility [patent_app_number] => 16/567919 [patent_app_country] => US [patent_app_date] => 2019-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11410 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16567919 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/567919
Memory cell array having three-dimensional structure Sep 10, 2019 Issued
Array ( [id] => 15331061 [patent_doc_number] => 20200005860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => SEMICONDUCTOR DEVICE FOR SELECTIVELY PERFORMING ISOLATION FUNCTION AND LAYOUT DISPLACEMENT METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/566002 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12468 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566002 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/566002
Semiconductor device for selectively performing isolation function and layout displacement method thereof Sep 9, 2019 Issued
Array ( [id] => 15331061 [patent_doc_number] => 20200005860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => SEMICONDUCTOR DEVICE FOR SELECTIVELY PERFORMING ISOLATION FUNCTION AND LAYOUT DISPLACEMENT METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/566002 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12468 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566002 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/566002
Semiconductor device for selectively performing isolation function and layout displacement method thereof Sep 9, 2019 Issued
Array ( [id] => 15331061 [patent_doc_number] => 20200005860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => SEMICONDUCTOR DEVICE FOR SELECTIVELY PERFORMING ISOLATION FUNCTION AND LAYOUT DISPLACEMENT METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/566002 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12468 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566002 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/566002
Semiconductor device for selectively performing isolation function and layout displacement method thereof Sep 9, 2019 Issued
Array ( [id] => 15331061 [patent_doc_number] => 20200005860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => SEMICONDUCTOR DEVICE FOR SELECTIVELY PERFORMING ISOLATION FUNCTION AND LAYOUT DISPLACEMENT METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/566002 [patent_app_country] => US [patent_app_date] => 2019-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12468 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566002 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/566002
Semiconductor device for selectively performing isolation function and layout displacement method thereof Sep 9, 2019 Issued
Array ( [id] => 16180163 [patent_doc_number] => 20200227132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => MEMORY CHIP [patent_app_type] => utility [patent_app_number] => 16/564513 [patent_app_country] => US [patent_app_date] => 2019-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9803 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16564513 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/564513
Memory system with controller and memory chips, where controller can change a set value read level and instruct memory chip to execute read operation with the changed set value Sep 8, 2019 Issued
Array ( [id] => 16000357 [patent_doc_number] => 20200176049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/564837 [patent_app_country] => US [patent_app_date] => 2019-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6817 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16564837 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/564837
Memory system with minimized heat generation which includes memory that operates at cryogenic temperature Sep 8, 2019 Issued
Array ( [id] => 17165946 [patent_doc_number] => 11152054 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-19 [patent_title] => Apparatuses and methods for performing background operations in memory using sensing circuitry [patent_app_type] => utility [patent_app_number] => 16/553313 [patent_app_country] => US [patent_app_date] => 2019-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6223 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16553313 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/553313
Apparatuses and methods for performing background operations in memory using sensing circuitry Aug 27, 2019 Issued
Array ( [id] => 16677481 [patent_doc_number] => 20210066247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => STACKED DIE PACKAGE INCLUDING WIRE BONDING AND DIRECT CHIP ATTACHMENT, AND RELATED METHODS, DEVICES AND APPARATUSES [patent_app_type] => utility [patent_app_number] => 16/553549 [patent_app_country] => US [patent_app_date] => 2019-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7906 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16553549 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/553549
Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding and related methods, devices and apparatuses Aug 27, 2019 Issued
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