| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 15331061
[patent_doc_number] => 20200005860
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-01-02
[patent_title] => SEMICONDUCTOR DEVICE FOR SELECTIVELY PERFORMING ISOLATION FUNCTION AND LAYOUT DISPLACEMENT METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/566002
[patent_app_country] => US
[patent_app_date] => 2019-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12468
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 320
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16566002
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/566002 | Semiconductor device for selectively performing isolation function and layout displacement method thereof | Sep 9, 2019 | Issued |
Array
(
[id] => 16180163
[patent_doc_number] => 20200227132
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-16
[patent_title] => MEMORY CHIP
[patent_app_type] => utility
[patent_app_number] => 16/564513
[patent_app_country] => US
[patent_app_date] => 2019-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9803
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16564513
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/564513 | Memory system with controller and memory chips, where controller can change a set value read level and instruct memory chip to execute read operation with the changed set value | Sep 8, 2019 | Issued |
Array
(
[id] => 16000357
[patent_doc_number] => 20200176049
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-04
[patent_title] => MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 16/564837
[patent_app_country] => US
[patent_app_date] => 2019-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6817
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16564837
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/564837 | Memory system with minimized heat generation which includes memory that operates at cryogenic temperature | Sep 8, 2019 | Issued |
Array
(
[id] => 16677481
[patent_doc_number] => 20210066247
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-04
[patent_title] => STACKED DIE PACKAGE INCLUDING WIRE BONDING AND DIRECT CHIP ATTACHMENT, AND RELATED METHODS, DEVICES AND APPARATUSES
[patent_app_type] => utility
[patent_app_number] => 16/553549
[patent_app_country] => US
[patent_app_date] => 2019-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7906
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -27
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16553549
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/553549 | Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding and related methods, devices and apparatuses | Aug 27, 2019 | Issued |
Array
(
[id] => 17165946
[patent_doc_number] => 11152054
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-10-19
[patent_title] => Apparatuses and methods for performing background operations in memory using sensing circuitry
[patent_app_type] => utility
[patent_app_number] => 16/553313
[patent_app_country] => US
[patent_app_date] => 2019-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6223
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16553313
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/553313 | Apparatuses and methods for performing background operations in memory using sensing circuitry | Aug 27, 2019 | Issued |
Array
(
[id] => 16409771
[patent_doc_number] => 10818333
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-10-27
[patent_title] => Circuitry for one-transistor synapse cell and operation method of the same
[patent_app_type] => utility
[patent_app_number] => 16/550809
[patent_app_country] => US
[patent_app_date] => 2019-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 6266
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 212
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16550809
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/550809 | Circuitry for one-transistor synapse cell and operation method of the same | Aug 25, 2019 | Issued |
Array
(
[id] => 16707461
[patent_doc_number] => 10957403
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-23
[patent_title] => Semiconductor device including a voltage generation circuit configured with first and second current circuits for increasing voltages of first, second, and third output nodes
[patent_app_type] => utility
[patent_app_number] => 16/549395
[patent_app_country] => US
[patent_app_date] => 2019-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 11620
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16549395
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/549395 | Semiconductor device including a voltage generation circuit configured with first and second current circuits for increasing voltages of first, second, and third output nodes | Aug 22, 2019 | Issued |
Array
(
[id] => 16660375
[patent_doc_number] => 20210057012
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-25
[patent_title] => APPARATUS AND METHOD INCLUDING ANALOG ACCUMULATOR FOR DETERMINING ROW ACCESS RATE AND TARGET ROW ADDRESS USED FOR REFRESH OPERATION
[patent_app_type] => utility
[patent_app_number] => 16/548027
[patent_app_country] => US
[patent_app_date] => 2019-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12972
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16548027
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/548027 | Apparatus and method including analog accumulator for determining row access rate and target row address used for refresh operation | Aug 21, 2019 | Issued |
Array
(
[id] => 16684168
[patent_doc_number] => 10943657
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-03-09
[patent_title] => Mitigation of voltage threshold drift associated with power down condition of non-volatile memory device
[patent_app_type] => utility
[patent_app_number] => 16/544669
[patent_app_country] => US
[patent_app_date] => 2019-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 14515
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16544669
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/544669 | Mitigation of voltage threshold drift associated with power down condition of non-volatile memory device | Aug 18, 2019 | Issued |
Array
(
[id] => 17152271
[patent_doc_number] => 11145358
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-10-12
[patent_title] => Offsetting capacitance of a digit line coupled to storage memory cells coupled to a sense amplifier using offset memory cells
[patent_app_type] => utility
[patent_app_number] => 16/543315
[patent_app_country] => US
[patent_app_date] => 2019-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 7582
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16543315
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/543315 | Offsetting capacitance of a digit line coupled to storage memory cells coupled to a sense amplifier using offset memory cells | Aug 15, 2019 | Issued |
Array
(
[id] => 16631388
[patent_doc_number] => 20210050041
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-18
[patent_title] => APPARATUSES AND METHODS FOR SETTING OPERATIONAL PARAMETERS OF A MEMORY INCLUDED IN A MEMORY MODULE BASED ON LOCATION INFORMATION
[patent_app_type] => utility
[patent_app_number] => 16/541097
[patent_app_country] => US
[patent_app_date] => 2019-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14485
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -24
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16541097
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/541097 | Apparatuses and methods for setting operational parameters of a memory included in a memory module based on location information | Aug 13, 2019 | Issued |
Array
(
[id] => 15184345
[patent_doc_number] => 20190362764
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-28
[patent_title] => FLEXIBLE DLL (DELAY LOCKED LOOP) CALIBRATION
[patent_app_type] => utility
[patent_app_number] => 16/538658
[patent_app_country] => US
[patent_app_date] => 2019-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11713
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16538658
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/538658 | Flexible DLL (delay locked loop) calibration | Aug 11, 2019 | Issued |
Array
(
[id] => 16502298
[patent_doc_number] => 10867692
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-15
[patent_title] => Apparatuses and methods for latching redundancy repair addresses at a memory
[patent_app_type] => utility
[patent_app_number] => 16/538572
[patent_app_country] => US
[patent_app_date] => 2019-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 7451
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16538572
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/538572 | Apparatuses and methods for latching redundancy repair addresses at a memory | Aug 11, 2019 | Issued |
Array
(
[id] => 15184375
[patent_doc_number] => 20190362779
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-28
[patent_title] => RANDOM-ACCESS MEMORY AND ASSOCIATED CIRCUIT, METHOD AND DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/537615
[patent_app_country] => US
[patent_app_date] => 2019-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12787
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16537615
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/537615 | Trigger and access circuitry for RAM to overcome instability of storage status and reduce power consumption | Aug 10, 2019 | Issued |
Array
(
[id] => 16746225
[patent_doc_number] => 10971225
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-04-06
[patent_title] => Resistive random access memory device with three-dimensional cross-point structure and method of operating the same
[patent_app_type] => utility
[patent_app_number] => 16/535712
[patent_app_country] => US
[patent_app_date] => 2019-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 25
[patent_no_of_words] => 7441
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16535712
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/535712 | Resistive random access memory device with three-dimensional cross-point structure and method of operating the same | Aug 7, 2019 | Issued |
Array
(
[id] => 16132021
[patent_doc_number] => 10699777
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-06-30
[patent_title] => Access device and associated storage device for performing rewrite operation based on trigger level
[patent_app_type] => utility
[patent_app_number] => 16/533755
[patent_app_country] => US
[patent_app_date] => 2019-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 23
[patent_no_of_words] => 12369
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16533755
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/533755 | Access device and associated storage device for performing rewrite operation based on trigger level | Aug 5, 2019 | Issued |
Array
(
[id] => 15217427
[patent_doc_number] => 20190371400
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-05
[patent_title] => HIGH-PERFORMANCE ON-MODULE CACHING ARCHITECTURES FOR NON-VOLATILE DUAL IN-LINE MEMORY MODULE (NVDIMM)
[patent_app_type] => utility
[patent_app_number] => 16/533278
[patent_app_country] => US
[patent_app_date] => 2019-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9598
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16533278
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/533278 | High-performance on-module caching architectures for non-volatile dual in-line memory module (NVDIMM) | Aug 5, 2019 | Issued |
Array
(
[id] => 16324002
[patent_doc_number] => 10783972
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-22
[patent_title] => NAND flash memory with reconfigurable neighbor assisted LLR correction with downsampling and pipelining
[patent_app_type] => utility
[patent_app_number] => 16/528321
[patent_app_country] => US
[patent_app_date] => 2019-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 18
[patent_no_of_words] => 11053
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16528321
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/528321 | NAND flash memory with reconfigurable neighbor assisted LLR correction with downsampling and pipelining | Jul 30, 2019 | Issued |
Array
(
[id] => 16097859
[patent_doc_number] => 20200202916
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-25
[patent_title] => MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/522121
[patent_app_country] => US
[patent_app_date] => 2019-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11472
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16522121
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/522121 | Memory device with memory cell structure including ferroelectric data storage layer, and a first gate and a second gate | Jul 24, 2019 | Issued |
Array
(
[id] => 16495509
[patent_doc_number] => 10861556
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-08
[patent_title] => Method and system for adapting solid state memory write parameters to satisfy performance goals based on degree of read errors
[patent_app_type] => utility
[patent_app_number] => 16/520263
[patent_app_country] => US
[patent_app_date] => 2019-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 7299
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16520263
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/520263 | Method and system for adapting solid state memory write parameters to satisfy performance goals based on degree of read errors | Jul 22, 2019 | Issued |