Search

Mushfique Siddique

Examiner (ID: 16359, Phone: (571)270-0424 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
838
Issued Applications
687
Pending Applications
93
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16379101 [patent_doc_number] => 20200327944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-15 [patent_title] => METHOD OF FAST ERASING AN EEPROM WITH LOW-VOLTAGES, WHERE IONS ARE IMPLANTED AT A HIGHER CONCENTRATION TO INCREASE THE INTENSITY OF THE ELECTRIC FIELD BETWEEN THE GATE AND THE SUBSTRATE OR BETWEEN THE GATE AND THE TRANSISTOR AND THUS DECREASE THE REQUIRED VOLTAGE DIFFERENCE FOR ERASING THE EEPROM [patent_app_type] => utility [patent_app_number] => 16/381193 [patent_app_country] => US [patent_app_date] => 2019-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3663 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16381193 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/381193
METHOD OF FAST ERASING AN EEPROM WITH LOW-VOLTAGES, WHERE IONS ARE IMPLANTED AT A HIGHER CONCENTRATION TO INCREASE THE INTENSITY OF THE ELECTRIC FIELD BETWEEN THE GATE AND THE SUBSTRATE OR BETWEEN THE GATE AND THE TRANSISTOR AND THUS DECREASE THE REQUIRED VOLTAGE DIFFERENCE FOR ERASING THE EEPROM Apr 10, 2019 Abandoned
Array ( [id] => 14676013 [patent_doc_number] => 20190237121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => FERROELECTRIC MEMORY AND CAPACITOR STRUCTURE THEREOF [patent_app_type] => utility [patent_app_number] => 16/380150 [patent_app_country] => US [patent_app_date] => 2019-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12656 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16380150 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/380150
Ferroelectric memory and capacitor structure thereof Apr 9, 2019 Issued
Array ( [id] => 15563807 [patent_doc_number] => 20200066315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/378926 [patent_app_country] => US [patent_app_date] => 2019-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9924 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16378926 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/378926
Resistive memory device and method for minimizing time for set program operation Apr 8, 2019 Issued
Array ( [id] => 16306649 [patent_doc_number] => 10775433 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-15 [patent_title] => Programmable/configurable logic circuitry, control circuitry and method of dynamic context switching [patent_app_type] => utility [patent_app_number] => 16/369809 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9012 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16369809 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/369809
Programmable/configurable logic circuitry, control circuitry and method of dynamic context switching Mar 28, 2019 Issued
Array ( [id] => 16802549 [patent_doc_number] => 10997498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Apparatus and method for in-memory binary convolution for accelerating deep binary neural networks based on a non-volatile memory structure [patent_app_type] => utility [patent_app_number] => 16/366187 [patent_app_country] => US [patent_app_date] => 2019-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3448 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16366187 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/366187
Apparatus and method for in-memory binary convolution for accelerating deep binary neural networks based on a non-volatile memory structure Mar 26, 2019 Issued
Array ( [id] => 16332017 [patent_doc_number] => 20200302983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-24 [patent_title] => MRAM ARRAY HAVING REFERENCE CELL STRUCTURE AND CIRCUITRY THAT REINFORCES REFERENCE STATES BY INDUCED MAGNETIC FIELD [patent_app_type] => utility [patent_app_number] => 16/362329 [patent_app_country] => US [patent_app_date] => 2019-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4977 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16362329 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/362329
MRAM array having reference cell structure and circuitry that reinforces reference states by induced magnetic field Mar 21, 2019 Issued
Array ( [id] => 16323976 [patent_doc_number] => 10783946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-22 [patent_title] => Semiconductor memory device including memory cell arrays [patent_app_type] => utility [patent_app_number] => 16/352483 [patent_app_country] => US [patent_app_date] => 2019-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 40 [patent_no_of_words] => 12419 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16352483 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/352483
Semiconductor memory device including memory cell arrays Mar 12, 2019 Issued
Array ( [id] => 15624939 [patent_doc_number] => 20200082874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/294169 [patent_app_country] => US [patent_app_date] => 2019-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16294169 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/294169
SEMICONDUCTOR MEMORY DEVICE Mar 5, 2019 Abandoned
Array ( [id] => 14508893 [patent_doc_number] => 20190198101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-27 [patent_title] => PHASE CHANGE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/291802 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291802 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/291802
Phase change memory device capable of selecting memory cells with different addresses for a reference mat and non-reference mats Mar 3, 2019 Issued
Array ( [id] => 15656467 [patent_doc_number] => 20200090764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-19 [patent_title] => SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM, AND METHOD [patent_app_type] => utility [patent_app_number] => 16/291473 [patent_app_country] => US [patent_app_date] => 2019-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16291473 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/291473
SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM, AND METHOD Mar 3, 2019 Abandoned
Array ( [id] => 15687533 [patent_doc_number] => 20200098430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => CAM MACRO CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/289809 [patent_app_country] => US [patent_app_date] => 2019-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3822 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16289809 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/289809
CAM MACRO CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT Feb 28, 2019 Abandoned
Array ( [id] => 16495458 [patent_doc_number] => 10861505 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => Nonvolatile memory apparatus for mitigating snap-back disturbance, and read and write method of the nonvolatile memory apparatus [patent_app_type] => utility [patent_app_number] => 16/289981 [patent_app_country] => US [patent_app_date] => 2019-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 9176 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16289981 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/289981
Nonvolatile memory apparatus for mitigating snap-back disturbance, and read and write method of the nonvolatile memory apparatus Feb 28, 2019 Issued
Array ( [id] => 16285991 [patent_doc_number] => 20200279593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-03 [patent_title] => REDUCING MEMORY POWER CONSUMPTION [patent_app_type] => utility [patent_app_number] => 16/289973 [patent_app_country] => US [patent_app_date] => 2019-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16289973 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/289973
RAM memory with pre-charging circuitry coupled to global bit-lines and method for reducing power consumption Feb 28, 2019 Issued
Array ( [id] => 16432658 [patent_doc_number] => 10832750 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Perpendicular spin transfer torque MRAM memory cell with cap layer to achieve lower current density and increased write margin [patent_app_type] => utility [patent_app_number] => 16/283625 [patent_app_country] => US [patent_app_date] => 2019-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6527 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16283625 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/283625
Perpendicular spin transfer torque MRAM memory cell with cap layer to achieve lower current density and increased write margin Feb 21, 2019 Issued
Array ( [id] => 15598285 [patent_doc_number] => 20200075677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/281275 [patent_app_country] => US [patent_app_date] => 2019-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6623 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16281275 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/281275
Convolutional neural network system employing resistance change memory cell array Feb 20, 2019 Issued
Array ( [id] => 17582584 [patent_doc_number] => 20220139439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => SEMICONDUCTOR MODULE, SEMICONDUCTOR MEMBER, AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/427520 [patent_app_country] => US [patent_app_date] => 2019-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7565 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17427520 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/427520
Three-dimensional semiconductor module including system in a package (SIP) with improved heat dissipation efficiency Jan 29, 2019 Issued
Array ( [id] => 16210132 [patent_doc_number] => 20200243122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => SRAM BASED PHYSICALLY UNCLONABLE FUNCTION AND METHOD FOR GENERATING A PUF RESPONSE [patent_app_type] => utility [patent_app_number] => 16/260751 [patent_app_country] => US [patent_app_date] => 2019-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16260751 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/260751
SRAM based physically unclonable function and method for generating a PUF response Jan 28, 2019 Issued
Array ( [id] => 14413353 [patent_doc_number] => 20190172520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-06 [patent_title] => Apparatuses Having Compensator Lines Along Wordlines and Independently Controlled Relative to the Wordlines [patent_app_type] => utility [patent_app_number] => 16/250919 [patent_app_country] => US [patent_app_date] => 2019-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3819 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16250919 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/250919
Apparatuses having compensator lines along wordlines and independently controlled relative to the wordlines Jan 16, 2019 Issued
Array ( [id] => 16667704 [patent_doc_number] => 10936953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => DNA-based digital information storage with sidewall electrodes [patent_app_type] => utility [patent_app_number] => 16/239453 [patent_app_country] => US [patent_app_date] => 2019-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 27 [patent_no_of_words] => 25374 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16239453 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/239453
DNA-based digital information storage with sidewall electrodes Jan 2, 2019 Issued
Array ( [id] => 16218242 [patent_doc_number] => 10734062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Semiconductor device with array configuration including upper segment, lower segment classified according to refresh units, repair controllers for controlling repair operation of upper segment and lower segment [patent_app_type] => utility [patent_app_number] => 16/219663 [patent_app_country] => US [patent_app_date] => 2018-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6236 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16219663 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/219663
Semiconductor device with array configuration including upper segment, lower segment classified according to refresh units, repair controllers for controlling repair operation of upper segment and lower segment Dec 12, 2018 Issued
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