Search

Mushfique Siddique

Examiner (ID: 1672, Phone: (571)270-0424 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
886
Issued Applications
722
Pending Applications
91
Abandoned Applications
88

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19634321 [patent_doc_number] => 20240412770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => SEQUENCED ACTIVATION OF MEMORY COMPONENTS [patent_app_type] => utility [patent_app_number] => 18/677571 [patent_app_country] => US [patent_app_date] => 2024-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10468 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677571 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/677571
SEQUENCED ACTIVATION OF MEMORY COMPONENTS May 28, 2024 Pending
Array ( [id] => 19452371 [patent_doc_number] => 20240312501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => BIT LINE LOGIC CIRCUIT AND METHOD [patent_app_type] => utility [patent_app_number] => 18/675770 [patent_app_country] => US [patent_app_date] => 2024-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12178 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675770 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/675770
Bit line logic circuit and method May 27, 2024 Issued
Array ( [id] => 20495184 [patent_doc_number] => 12537060 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Programming delay scheme for in a memory sub-system based on memory reliability [patent_app_type] => utility [patent_app_number] => 18/666063 [patent_app_country] => US [patent_app_date] => 2024-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 10892 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18666063 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/666063
Programming delay scheme for in a memory sub-system based on memory reliability May 15, 2024 Issued
Array ( [id] => 19420761 [patent_doc_number] => 20240296885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => MEMORY SELECTOR THRESHOLD VOLTAGE RECOVERY [patent_app_type] => utility [patent_app_number] => 18/661902 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8476 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18661902 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/661902
Memory selector threshold voltage recovery May 12, 2024 Issued
Array ( [id] => 19420763 [patent_doc_number] => 20240296887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => NON-VOLATILE STATIC RANDOM ACCESS MEMORY (NVSRAM) WITH MULTIPLE MAGNETIC TUNNEL JUNCTION CELLS [patent_app_type] => utility [patent_app_number] => 18/662806 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9963 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18662806 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/662806
Non-volatile static random access memory (NVSRAM) with multiple magnetic tunnel junction cells May 12, 2024 Issued
Array ( [id] => 20923802 [patent_doc_number] => 12718868 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-25 [patent_title] => Three-dimensional memory devices and fabricating methods thereof [patent_app_type] => utility [patent_app_number] => 18/660852 [patent_app_country] => US [patent_app_date] => 2024-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 7436 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18660852 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/660852
THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF May 9, 2024 Pending
Array ( [id] => 19406895 [patent_doc_number] => 20240290406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => MEMORY DEVICE WEAR LEVELING [patent_app_type] => utility [patent_app_number] => 18/655700 [patent_app_country] => US [patent_app_date] => 2024-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10179 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18655700 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/655700
Memory device wear leveling May 5, 2024 Issued
Array ( [id] => 19618906 [patent_doc_number] => 20240404586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => VOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/651072 [patent_app_country] => US [patent_app_date] => 2024-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11093 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18651072 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/651072
Volatile memory device with global input and output line allocated for metadata Apr 29, 2024 Issued
Array ( [id] => 20774561 [patent_doc_number] => 12658240 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-16 [patent_title] => Compute in memory (CIM) memory array for storing weights [patent_app_type] => utility [patent_app_number] => 18/643832 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643832 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/643832
Compute in memory (CIM) memory array for storing weights Apr 22, 2024 Issued
Array ( [id] => 19618896 [patent_doc_number] => 20240404576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => Control Circuitry for Scheduling Aspects of Usage-Based Disturbance Mitigation Based on Different External Commands [patent_app_type] => utility [patent_app_number] => 18/642144 [patent_app_country] => US [patent_app_date] => 2024-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9480 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18642144 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/642144
Control Circuitry for Scheduling Aspects of Usage-Based Disturbance Mitigation Based on Different External Commands Apr 21, 2024 Pending
Array ( [id] => 20088565 [patent_doc_number] => 20250218501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => MEMORY DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 18/638247 [patent_app_country] => US [patent_app_date] => 2024-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18638247 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/638247
MEMORY DEVICE AND METHOD Apr 16, 2024 Pending
Array ( [id] => 20258841 [patent_doc_number] => 12431204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Memory device and program operation thereof [patent_app_type] => utility [patent_app_number] => 18/636569 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 8128 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18636569 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/636569
Memory device and program operation thereof Apr 15, 2024 Issued
Array ( [id] => 19351295 [patent_doc_number] => 20240260259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE HAVING FUSE ELEMENTS [patent_app_type] => utility [patent_app_number] => 18/635365 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9235 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635365 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635365
Semiconductor device structure having fuse elements Apr 14, 2024 Issued
Array ( [id] => 20297622 [patent_doc_number] => 20250322865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => GAIN CELL MEMORY DEVICE USING ENHANCED SENSING SCHEME AND METHODS FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/633847 [patent_app_country] => US [patent_app_date] => 2024-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9783 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18633847 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/633847
Gain cell memory device using enhanced sensing scheme and methods for operating the same Apr 11, 2024 Issued
Array ( [id] => 20636577 [patent_doc_number] => 12597458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-07 [patent_title] => Write leveling in DDR memory device and operating method thereof [patent_app_type] => utility [patent_app_number] => 18/629906 [patent_app_country] => US [patent_app_date] => 2024-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18629906 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/629906
Write leveling in DDR memory device and operating method thereof Apr 7, 2024 Issued
Array ( [id] => 19348922 [patent_doc_number] => 20240257886 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/626748 [patent_app_country] => US [patent_app_date] => 2024-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19303 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18626748 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/626748
Memory device preventing generation of under-programmed memory cell, memory system including the same and operating method thereof Apr 3, 2024 Issued
Array ( [id] => 20732930 [patent_doc_number] => 12640190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Memory circuit with level shifter circuit and method of operating same [patent_app_type] => utility [patent_app_number] => 18/624551 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7328 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 345 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18624551 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/624551
Memory circuit with level shifter circuit and method of operating same Apr 1, 2024 Issued
Array ( [id] => 20036046 [patent_doc_number] => 20250174268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => MEMORY DEVICES AND OPERATING METHODS THEREOF, MEMORY SYSTEMS, AND SENSING CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/614078 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5916 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614078 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/614078
MEMORY DEVICES AND OPERATING METHODS THEREOF, MEMORY SYSTEMS, AND SENSING CIRCUITS Mar 21, 2024 Pending
Array ( [id] => 20019300 [patent_doc_number] => 20250157522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => SEMICONDUCTOR DEVICES RELATED TO THE GENERATION OF A COMMAND [patent_app_type] => utility [patent_app_number] => 18/610896 [patent_app_country] => US [patent_app_date] => 2024-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2336 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18610896 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/610896
Semiconductor devices including a clock divider related to the generation of a command Mar 19, 2024 Issued
Array ( [id] => 19452383 [patent_doc_number] => 20240312513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/600715 [patent_app_country] => US [patent_app_date] => 2024-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20479 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18600715 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/600715
SEMICONDUCTOR MEMORY DEVICE Mar 9, 2024 Pending
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