Search

Mushfique Siddique

Examiner (ID: 16359, Phone: (571)270-0424 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
838
Issued Applications
687
Pending Applications
93
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13908799 [patent_doc_number] => 20190043604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => MULTI-LEVEL MEMORY REPURPOSING [patent_app_type] => utility [patent_app_number] => 16/107155 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9668 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16107155 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/107155
Multi-level memory repurposing technology to process a request to modify a configuration of a persistent storage media Aug 20, 2018 Issued
Array ( [id] => 16201741 [patent_doc_number] => 10726916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Resistive memory device with trimmable driver and sinker and method of operations thereof [patent_app_type] => utility [patent_app_number] => 16/105527 [patent_app_country] => US [patent_app_date] => 2018-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 9099 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16105527 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/105527
Resistive memory device with trimmable driver and sinker and method of operations thereof Aug 19, 2018 Issued
Array ( [id] => 13613101 [patent_doc_number] => 20180358100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-13 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/105078 [patent_app_country] => US [patent_app_date] => 2018-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19229 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16105078 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/105078
Memory system Aug 19, 2018 Issued
Array ( [id] => 15702993 [patent_doc_number] => 10607683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Semiconductor memory device capable of performing a hammer refresh operation while performing a normal refresh operation and memory system having the same [patent_app_type] => utility [patent_app_number] => 16/059791 [patent_app_country] => US [patent_app_date] => 2018-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8067 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16059791 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/059791
Semiconductor memory device capable of performing a hammer refresh operation while performing a normal refresh operation and memory system having the same Aug 8, 2018 Issued
Array ( [id] => 16668220 [patent_doc_number] => 10937473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => Clock signal drivers for read and write memory operations [patent_app_type] => utility [patent_app_number] => 16/058687 [patent_app_country] => US [patent_app_date] => 2018-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4843 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16058687 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/058687
Clock signal drivers for read and write memory operations Aug 7, 2018 Issued
Array ( [id] => 15580139 [patent_doc_number] => 10580461 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => Semiconductor memory device and layout scheme of global lines over pass transistors [patent_app_type] => utility [patent_app_number] => 16/054465 [patent_app_country] => US [patent_app_date] => 2018-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9046 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16054465 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/054465
Semiconductor memory device and layout scheme of global lines over pass transistors Aug 2, 2018 Issued
Array ( [id] => 15518881 [patent_doc_number] => 10566034 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-02-18 [patent_title] => Memory device with control and test circuit, and method for test reading and writing using bit line precharge voltage levels [patent_app_type] => utility [patent_app_number] => 16/045759 [patent_app_country] => US [patent_app_date] => 2018-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7717 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16045759 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/045759
Memory device with control and test circuit, and method for test reading and writing using bit line precharge voltage levels Jul 25, 2018 Issued
Array ( [id] => 14445923 [patent_doc_number] => 20190180835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => MEMORY DEVICE, OPERATING METHOD OF MEMORY DEVICE, AND OPERATING METHOD OF TEST SYSTEM INCLUDING MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/046453 [patent_app_country] => US [patent_app_date] => 2018-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8227 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16046453 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/046453
Memory device with test circuit which generates asychronous signal based on delay and controls peripheral circuit based on asynchronous signal, operating method of memory device, and operating method of test system including memory device Jul 25, 2018 Issued
Array ( [id] => 15442239 [patent_doc_number] => 20200035303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => NON-VOLATILE STATIC RANDOM ACCESS MEMORY ARCHITECTURE HAVING SINGLE NON-VOLATILE BIT PER VOLATILE MEMORY BIT [patent_app_type] => utility [patent_app_number] => 16/043425 [patent_app_country] => US [patent_app_date] => 2018-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16043425 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/043425
Non-volatile static random access memory architecture having single non-volatile bit per volatile memory bit Jul 23, 2018 Issued
Array ( [id] => 16308469 [patent_doc_number] => 10777274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Semiconductor memory system with resistive variable memory device having scheduler for changing generation period of command and driving method thereof [patent_app_type] => utility [patent_app_number] => 16/029088 [patent_app_country] => US [patent_app_date] => 2018-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 32 [patent_no_of_words] => 10662 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16029088 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/029088
Semiconductor memory system with resistive variable memory device having scheduler for changing generation period of command and driving method thereof Jul 5, 2018 Issued
Array ( [id] => 15331063 [patent_doc_number] => 20200005861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => MULTI-LEVEL MAGNETIC TUNNEL JUNCTION (MTJ) DEVICES [patent_app_type] => utility [patent_app_number] => 16/022547 [patent_app_country] => US [patent_app_date] => 2018-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16022547 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/022547
Multi-level magnetic tunnel junction (MTJ) devices including mobile magnetic skyrmions or ferromagnetic domains Jun 27, 2018 Issued
Array ( [id] => 14858713 [patent_doc_number] => 10418090 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-09-17 [patent_title] => Write signal launch circuitry for memory drive [patent_app_type] => utility [patent_app_number] => 16/014539 [patent_app_country] => US [patent_app_date] => 2018-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5956 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16014539 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/014539
Write signal launch circuitry for memory drive Jun 20, 2018 Issued
Array ( [id] => 16536266 [patent_doc_number] => 10878879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Refresh control method for memory system to perform refresh action on all memory banks of the memory system within refresh window [patent_app_type] => utility [patent_app_number] => 16/011779 [patent_app_country] => US [patent_app_date] => 2018-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 5020 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16011779 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/011779
Refresh control method for memory system to perform refresh action on all memory banks of the memory system within refresh window Jun 18, 2018 Issued
Array ( [id] => 15077219 [patent_doc_number] => 10468104 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-11-05 [patent_title] => Robust and error free physical unclonable function using twin-cell charge trap transistor memory [patent_app_type] => utility [patent_app_number] => 16/007445 [patent_app_country] => US [patent_app_date] => 2018-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5167 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16007445 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/007445
Robust and error free physical unclonable function using twin-cell charge trap transistor memory Jun 12, 2018 Issued
Array ( [id] => 14735299 [patent_doc_number] => 10387048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Memory devices configured to latch data for output in response to an edge of a clock signal generated in response to an edge of another clock signal [patent_app_type] => utility [patent_app_number] => 16/006192 [patent_app_country] => US [patent_app_date] => 2018-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9689 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16006192 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/006192
Memory devices configured to latch data for output in response to an edge of a clock signal generated in response to an edge of another clock signal Jun 11, 2018 Issued
Array ( [id] => 13484969 [patent_doc_number] => 20180294027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => APPARATUSES AND METHODS FOR LOGIC/MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/004864 [patent_app_country] => US [patent_app_date] => 2018-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13780 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16004864 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/004864
Processing in memory (PIM) capable memory device having timing circuitry to control timing of operations Jun 10, 2018 Issued
Array ( [id] => 13469903 [patent_doc_number] => 20180286494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => ARRAY PLATE SHORT REPAIR [patent_app_type] => utility [patent_app_number] => 16/001784 [patent_app_country] => US [patent_app_date] => 2018-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29052 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16001784 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/001784
Array plate short repair Jun 5, 2018 Issued
Array ( [id] => 14237553 [patent_doc_number] => 20190130949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 15/989609 [patent_app_country] => US [patent_app_date] => 2018-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10079 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15989609 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/989609
Semiconductor memory apparatus with memory banks and semiconductor system including the same May 24, 2018 Issued
Array ( [id] => 13434705 [patent_doc_number] => 20180268895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => Method and Circuit to Enable Wide Supply Voltage Difference in Multi-Supply Memory [patent_app_type] => utility [patent_app_number] => 15/988140 [patent_app_country] => US [patent_app_date] => 2018-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7256 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15988140 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/988140
Method and circuit to enable wide supply voltage difference in multi-supply memory May 23, 2018 Issued
Array ( [id] => 15060961 [patent_doc_number] => 10460792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Synchronous dynamic random access memory (SDRAM) and memory controller device mounted in single system in package (SIP) [patent_app_type] => utility [patent_app_number] => 15/975886 [patent_app_country] => US [patent_app_date] => 2018-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 9544 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15975886 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/975886
Synchronous dynamic random access memory (SDRAM) and memory controller device mounted in single system in package (SIP) May 9, 2018 Issued
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