Search

Mushfique Siddique

Examiner (ID: 16359, Phone: (571)270-0424 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
838
Issued Applications
687
Pending Applications
93
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12263526 [patent_doc_number] => 20180082722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'NEGATIVE BITLINE WRITE ASSIST CIRCUIT AND METHOD FOR OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/809647 [patent_app_country] => US [patent_app_date] => 2017-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6021 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15809647 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/809647
Negative bitline write assist circuit and method for operating the same Nov 9, 2017 Issued
Array ( [id] => 16067183 [patent_doc_number] => 10692550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Tracking and correction of timing signals [patent_app_type] => utility [patent_app_number] => 15/808508 [patent_app_country] => US [patent_app_date] => 2017-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6980 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15808508 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/808508
Tracking and correction of timing signals Nov 8, 2017 Issued
Array ( [id] => 15611053 [patent_doc_number] => 10586593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Programmable resistive device and memory using diode as selector [patent_app_type] => utility [patent_app_number] => 15/805109 [patent_app_country] => US [patent_app_date] => 2017-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 14185 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15805109 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/805109
Programmable resistive device and memory using diode as selector Nov 5, 2017 Issued
Array ( [id] => 15169515 [patent_doc_number] => 10490260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/803313 [patent_app_country] => US [patent_app_date] => 2017-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5808 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15803313 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/803313
Semiconductor device Nov 2, 2017 Issued
Array ( [id] => 12235867 [patent_doc_number] => 20180068730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/798113 [patent_app_country] => US [patent_app_date] => 2017-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10694 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15798113 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/798113
Semiconductor memory device and method of operating the same Oct 29, 2017 Issued
Array ( [id] => 14135795 [patent_doc_number] => 20190102287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => REMOTE PERSISTENT MEMORY ACCESS DEVICE [patent_app_type] => utility [patent_app_number] => 15/720885 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13635 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15720885 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/720885
REMOTE PERSISTENT MEMORY ACCESS DEVICE Sep 28, 2017 Abandoned
Array ( [id] => 14109573 [patent_doc_number] => 20190096462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => ONE-TRANSISTOR SYNAPSE CELL WITH WEIGHT ADJUSTMENT [patent_app_type] => utility [patent_app_number] => 15/717023 [patent_app_country] => US [patent_app_date] => 2017-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15717023 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/717023
One-transistor synapse cell with weight adjustment Sep 26, 2017 Issued
Array ( [id] => 14798397 [patent_doc_number] => 10402202 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Pipe latch circuit which controls output of data in a read operation and data output circuit including the same [patent_app_type] => utility [patent_app_number] => 15/713781 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7299 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15713781 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/713781
Pipe latch circuit which controls output of data in a read operation and data output circuit including the same Sep 24, 2017 Issued
Array ( [id] => 12595110 [patent_doc_number] => 20180090200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => Quantum Metrology and Quantum Memory Using Defect States With Spin-3/2 or Higher Half-Spin Multiplets [patent_app_type] => utility [patent_app_number] => 15/712403 [patent_app_country] => US [patent_app_date] => 2017-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11215 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15712403 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/712403
Quantum metrology and quantum memory using defect states with spin-3/2 or higher half-spin multiplets Sep 21, 2017 Issued
Array ( [id] => 14429247 [patent_doc_number] => 10319437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Apparatus and method for identifying memory cells for data refresh based on monitor cell in a resistive memory device [patent_app_type] => utility [patent_app_number] => 15/710247 [patent_app_country] => US [patent_app_date] => 2017-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 13559 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15710247 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/710247
Apparatus and method for identifying memory cells for data refresh based on monitor cell in a resistive memory device Sep 19, 2017 Issued
Array ( [id] => 13392307 [patent_doc_number] => 20180247696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-30 [patent_title] => MEMORY SYSTEM COMPRISING NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 15/703747 [patent_app_country] => US [patent_app_date] => 2017-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22973 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15703747 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/703747
Controller, memory system, and block management method for NAND flash memory using the same Sep 12, 2017 Issued
Array ( [id] => 14049293 [patent_doc_number] => 20190080753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => Architectures and Layouts for an Array Of Resistive Random Access Memory Cells and Read and Write Methods Thereof [patent_app_type] => utility [patent_app_number] => 15/701071 [patent_app_country] => US [patent_app_date] => 2017-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11094 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -44 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15701071 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/701071
Architectures and layouts for an array of resistive random access memory cells and read and write methods thereof Sep 10, 2017 Issued
Array ( [id] => 12668203 [patent_doc_number] => 20180114567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-26 [patent_title] => Random-Access Memory and Associated Circuit, Method and System [patent_app_type] => utility [patent_app_number] => 15/694859 [patent_app_country] => US [patent_app_date] => 2017-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11914 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15694859 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/694859
1T1D DRAM cell and access method and associated device for DRAM Sep 3, 2017 Issued
Array ( [id] => 14827419 [patent_doc_number] => 10410720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-10 [patent_title] => Multi-layer resistive memory device with variable resistance elements [patent_app_type] => utility [patent_app_number] => 15/694957 [patent_app_country] => US [patent_app_date] => 2017-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 44 [patent_no_of_words] => 19746 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15694957 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/694957
Multi-layer resistive memory device with variable resistance elements Sep 3, 2017 Issued
Array ( [id] => 13995241 [patent_doc_number] => 20190066778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => PHASE CHANGE MEMORY APPARATUS AND READ CONTROL METHOD TO REDUCE READ DISTURB AND SNEAK CURRENT PHENOMENA [patent_app_type] => utility [patent_app_number] => 15/687687 [patent_app_country] => US [patent_app_date] => 2017-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10585 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687687 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/687687
Phase change memory apparatus and read control method to reduce read disturb and sneak current phenomena Aug 27, 2017 Issued
Array ( [id] => 16218245 [patent_doc_number] => 10734065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Providing a discharge boundary using bitline discharge control circuitry for an integrated circuit [patent_app_type] => utility [patent_app_number] => 15/684255 [patent_app_country] => US [patent_app_date] => 2017-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4999 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15684255 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/684255
Providing a discharge boundary using bitline discharge control circuitry for an integrated circuit Aug 22, 2017 Issued
Array ( [id] => 14706691 [patent_doc_number] => 10381103 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Apparatuses and methods for latching redundancy repair addresses to avoid address bits overwritten at a repair block [patent_app_type] => utility [patent_app_number] => 15/681183 [patent_app_country] => US [patent_app_date] => 2017-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7403 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15681183 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/681183
Apparatuses and methods for latching redundancy repair addresses to avoid address bits overwritten at a repair block Aug 17, 2017 Issued
Array ( [id] => 14557717 [patent_doc_number] => 10347326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Resistive memory apparatus with a single read/write driver [patent_app_type] => utility [patent_app_number] => 15/672697 [patent_app_country] => US [patent_app_date] => 2017-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4525 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15672697 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/672697
Resistive memory apparatus with a single read/write driver Aug 8, 2017 Issued
Array ( [id] => 12187071 [patent_doc_number] => 20180046007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'DISPLAY APPARATUS AND A METHOD OF DRIVING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/671415 [patent_app_country] => US [patent_app_date] => 2017-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10814 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15671415 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/671415
Display apparatus including data driving integrated circuits each including dummy data channels and a method of driving the same Aug 7, 2017 Issued
Array ( [id] => 12187648 [patent_doc_number] => 20180046584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'ADDRESS CONTROL CIRCUIT AND CONTROL METHOD FOR ADDRESS CONTROL CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/671267 [patent_app_country] => US [patent_app_date] => 2017-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4833 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15671267 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/671267
Address control circuit capable of setting address rapidly and method of setting address after power-on reset, the address control circuit providing protection against over-voltage Aug 7, 2017 Issued
Menu