Search

Mushfique Siddique

Examiner (ID: 1672, Phone: (571)270-0424 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
886
Issued Applications
722
Pending Applications
91
Abandoned Applications
88

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13469903 [patent_doc_number] => 20180286494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => ARRAY PLATE SHORT REPAIR [patent_app_type] => utility [patent_app_number] => 16/001784 [patent_app_country] => US [patent_app_date] => 2018-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29052 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16001784 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/001784
Array plate short repair Jun 5, 2018 Issued
Array ( [id] => 14237553 [patent_doc_number] => 20190130949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 15/989609 [patent_app_country] => US [patent_app_date] => 2018-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10079 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15989609 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/989609
Semiconductor memory apparatus with memory banks and semiconductor system including the same May 24, 2018 Issued
Array ( [id] => 13434705 [patent_doc_number] => 20180268895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => Method and Circuit to Enable Wide Supply Voltage Difference in Multi-Supply Memory [patent_app_type] => utility [patent_app_number] => 15/988140 [patent_app_country] => US [patent_app_date] => 2018-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7256 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15988140 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/988140
Method and circuit to enable wide supply voltage difference in multi-supply memory May 23, 2018 Issued
Array ( [id] => 15060961 [patent_doc_number] => 10460792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Synchronous dynamic random access memory (SDRAM) and memory controller device mounted in single system in package (SIP) [patent_app_type] => utility [patent_app_number] => 15/975886 [patent_app_country] => US [patent_app_date] => 2018-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 9544 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15975886 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/975886
Synchronous dynamic random access memory (SDRAM) and memory controller device mounted in single system in package (SIP) May 9, 2018 Issued
Array ( [id] => 16339054 [patent_doc_number] => 10790021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-29 [patent_title] => EEPROM, and methods for erasing, programming and reading the EEPROM [patent_app_type] => utility [patent_app_number] => 15/948487 [patent_app_country] => US [patent_app_date] => 2018-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7423 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15948487 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/948487
EEPROM, and methods for erasing, programming and reading the EEPROM Apr 8, 2018 Issued
Array ( [id] => 14366401 [patent_doc_number] => 10304512 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Ferroelectric memory, data reading/writing method and manufacturing method thereof and capacitor structure [patent_app_type] => utility [patent_app_number] => 15/942599 [patent_app_country] => US [patent_app_date] => 2018-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 39 [patent_no_of_words] => 13449 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15942599 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/942599
Ferroelectric memory, data reading/writing method and manufacturing method thereof and capacitor structure Apr 1, 2018 Issued
Array ( [id] => 15921535 [patent_doc_number] => 10658014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => Memory device with memory cell blocks, bit line sense amplifier blocks, and control circuit connected to bit line sense amplifier blocks to control constant levels of currents supplied to sensing driving voltage lines [patent_app_type] => utility [patent_app_number] => 15/941877 [patent_app_country] => US [patent_app_date] => 2018-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12580 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15941877 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/941877
Memory device with memory cell blocks, bit line sense amplifier blocks, and control circuit connected to bit line sense amplifier blocks to control constant levels of currents supplied to sensing driving voltage lines Mar 29, 2018 Issued
Array ( [id] => 14317843 [patent_doc_number] => 20190148625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => MAGNETIC RANDOM ACCESS MEMORY [patent_app_type] => utility [patent_app_number] => 15/940425 [patent_app_country] => US [patent_app_date] => 2018-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9960 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15940425 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/940425
Magnetic random access memory with various size magnetic tunneling junction film stacks Mar 28, 2018 Issued
Array ( [id] => 16502253 [patent_doc_number] => 10867646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-15 [patent_title] => Bit line logic circuits and methods [patent_app_type] => utility [patent_app_number] => 15/938393 [patent_app_country] => US [patent_app_date] => 2018-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 11280 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15938393 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/938393
Bit line logic circuits and methods Mar 27, 2018 Issued
Array ( [id] => 16249261 [patent_doc_number] => 10748635 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Dynamic power analysis with per-memory instance activity customization [patent_app_type] => utility [patent_app_number] => 15/928587 [patent_app_country] => US [patent_app_date] => 2018-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2865 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15928587 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/928587
Dynamic power analysis with per-memory instance activity customization Mar 21, 2018 Issued
Array ( [id] => 15672489 [patent_doc_number] => 10600483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-24 [patent_title] => Ternary content addressable memory with match line circuit for controlling potential of match realizing higher speed of search access [patent_app_type] => utility [patent_app_number] => 15/926863 [patent_app_country] => US [patent_app_date] => 2018-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 10871 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15926863 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/926863
Ternary content addressable memory with match line circuit for controlling potential of match realizing higher speed of search access Mar 19, 2018 Issued
Array ( [id] => 13419519 [patent_doc_number] => 20180261302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => PLATE DEFECT MITIGATION TECHNIQUES [patent_app_type] => utility [patent_app_number] => 15/913413 [patent_app_country] => US [patent_app_date] => 2018-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15913413 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/913413
Plate defect mitigation techniques Mar 5, 2018 Issued
Array ( [id] => 15822601 [patent_doc_number] => 10636494 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-28 [patent_title] => Apparatus and method for reducing noise generated from locked out sense circuits in a non-volatile memory system [patent_app_type] => utility [patent_app_number] => 15/908239 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 30 [patent_no_of_words] => 26092 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15908239 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/908239
Apparatus and method for reducing noise generated from locked out sense circuits in a non-volatile memory system Feb 27, 2018 Issued
Array ( [id] => 14109575 [patent_doc_number] => 20190096463 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => CIRCUITRY FOR ONE-TRANSISTOR SYNAPSE CELL AND OPERATION METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 15/859583 [patent_app_country] => US [patent_app_date] => 2017-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6249 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15859583 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/859583
One-transistor synapse cell with weight adjustment Dec 30, 2017 Issued
Array ( [id] => 16409765 [patent_doc_number] => 10818326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-27 [patent_title] => Negative bitline write assist circuit and method for operating the same [patent_app_type] => utility [patent_app_number] => 15/854549 [patent_app_country] => US [patent_app_date] => 2017-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5843 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15854549 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/854549
Negative bitline write assist circuit and method for operating the same Dec 25, 2017 Issued
Array ( [id] => 14475161 [patent_doc_number] => 20190189227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => STORAGE DEVICE AND ASSOCIATED CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 15/844849 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3717 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15844849 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/844849
Storage device and associated control method to determine target memory blocks for probe operation Dec 17, 2017 Issued
Array ( [id] => 14800757 [patent_doc_number] => 10403387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Repair circuit used in a memory device for performing error correction code operation and redundancy repair operation [patent_app_type] => utility [patent_app_number] => 15/843733 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8028 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15843733 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/843733
Repair circuit used in a memory device for performing error correction code operation and redundancy repair operation Dec 14, 2017 Issued
Array ( [id] => 14919957 [patent_doc_number] => 10431305 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-01 [patent_title] => High-performance on-module caching architectures for non-volatile dual in-line memory module (NVDIMM) [patent_app_type] => utility [patent_app_number] => 15/841997 [patent_app_country] => US [patent_app_date] => 2017-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9600 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15841997 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/841997
High-performance on-module caching architectures for non-volatile dual in-line memory module (NVDIMM) Dec 13, 2017 Issued
Array ( [id] => 14954809 [patent_doc_number] => 10438681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-08 [patent_title] => Test structures and test pads in scribe lane of semiconductor integrated circuit [patent_app_type] => utility [patent_app_number] => 15/840651 [patent_app_country] => US [patent_app_date] => 2017-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4157 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15840651 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/840651
Test structures and test pads in scribe lane of semiconductor integrated circuit Dec 12, 2017 Issued
Array ( [id] => 15061005 [patent_doc_number] => 10460814 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Non-volatile memory and method for power efficient read or verify using lockout control [patent_app_type] => utility [patent_app_number] => 15/838863 [patent_app_country] => US [patent_app_date] => 2017-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7306 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15838863 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/838863
Non-volatile memory and method for power efficient read or verify using lockout control Dec 11, 2017 Issued
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