Search

Mushfique Siddique

Examiner (ID: 16359, Phone: (571)270-0424 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
838
Issued Applications
687
Pending Applications
93
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14332579 [patent_doc_number] => 10297313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Phase change memory device capable of changing position of selected cell address [patent_app_type] => utility [patent_app_number] => 15/670823 [patent_app_country] => US [patent_app_date] => 2017-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3870 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15670823 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/670823
Phase change memory device capable of changing position of selected cell address Aug 6, 2017 Issued
Array ( [id] => 14738527 [patent_doc_number] => 10388674 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Apparatus and method for reducing the width of the frame in display device utilizing an inter-substrate connecting material [patent_app_type] => utility [patent_app_number] => 15/659799 [patent_app_country] => US [patent_app_date] => 2017-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 11889 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15659799 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/659799
Apparatus and method for reducing the width of the frame in display device utilizing an inter-substrate connecting material Jul 25, 2017 Issued
Array ( [id] => 16146211 [patent_doc_number] => 10706177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Apparatus and method for chip identification and preventing malicious manipulation of physical addresses by incorporating a physical network with a logical network [patent_app_type] => utility [patent_app_number] => 15/638564 [patent_app_country] => US [patent_app_date] => 2017-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 51 [patent_no_of_words] => 24165 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 366 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15638564 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/638564
Apparatus and method for chip identification and preventing malicious manipulation of physical addresses by incorporating a physical network with a logical network Jun 29, 2017 Issued
Array ( [id] => 13784961 [patent_doc_number] => 20190006019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => WORD LINE LEAKAGE DETECTION USING SOURCE AND SINK CURRENTS [patent_app_type] => utility [patent_app_number] => 15/636287 [patent_app_country] => US [patent_app_date] => 2017-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22033 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15636287 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/636287
WORD LINE LEAKAGE DETECTION USING SOURCE AND SINK CURRENTS Jun 27, 2017 Abandoned
Array ( [id] => 13784909 [patent_doc_number] => 20190005993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => GLOBAL BIT LINE PRE-CHARGING AND DATA LATCHING IN MULTI-BANKED MEMORIES USING A DELAYED RESET LATCH [patent_app_type] => utility [patent_app_number] => 15/635825 [patent_app_country] => US [patent_app_date] => 2017-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6270 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15635825 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/635825
Global bit line pre-charging and data latching in multi-banked memories using a delayed reset latch Jun 27, 2017 Issued
Array ( [id] => 13723611 [patent_doc_number] => 20170372761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-28 [patent_title] => Systems for Source Line Sensing of Magnetoelectric Junctions [patent_app_type] => utility [patent_app_number] => 15/636555 [patent_app_country] => US [patent_app_date] => 2017-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9132 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15636555 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/636555
Systems for Source Line Sensing of Magnetoelectric Junctions Jun 27, 2017 Abandoned
Array ( [id] => 14603069 [patent_doc_number] => 10354728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-16 [patent_title] => Write verification and resistive state determination based on cell turn-on characteristics for resistive random access memory [patent_app_type] => utility [patent_app_number] => 15/635935 [patent_app_country] => US [patent_app_date] => 2017-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 15467 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15635935 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/635935
Write verification and resistive state determination based on cell turn-on characteristics for resistive random access memory Jun 27, 2017 Issued
Array ( [id] => 13740123 [patent_doc_number] => 20180374531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => Apparatuses Having Compensator Lines Along Wordlines and Independently Controlled Relative to the Wordlines [patent_app_type] => utility [patent_app_number] => 15/633595 [patent_app_country] => US [patent_app_date] => 2017-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3791 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15633595 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/633595
Apparatuses with compensator lines laid out along wordlines and spaced apart from wordlines by dielectric, compensator lines being independently controlled relative to the wordlines providing increased on-current in wordlines, reduced leakage in coupled transistors and longer retention time in coupled memory cells Jun 25, 2017 Issued
Array ( [id] => 14603017 [patent_doc_number] => 10354702 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-16 [patent_title] => Semiconductor memory device with a control logic capable of controlling the ready busy output control unit to adjust an output current to be outputted to a ready/busy pad, and a method for operating the same [patent_app_type] => utility [patent_app_number] => 15/632591 [patent_app_country] => US [patent_app_date] => 2017-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 14003 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15632591 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/632591
Semiconductor memory device with a control logic capable of controlling the ready busy output control unit to adjust an output current to be outputted to a ready/busy pad, and a method for operating the same Jun 25, 2017 Issued
Array ( [id] => 14525491 [patent_doc_number] => 10340016 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Methods of error-based read disturb mitigation and memory devices utilizing the same [patent_app_type] => utility [patent_app_number] => 15/633377 [patent_app_country] => US [patent_app_date] => 2017-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7281 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15633377 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/633377
Methods of error-based read disturb mitigation and memory devices utilizing the same Jun 25, 2017 Issued
Array ( [id] => 12122118 [patent_doc_number] => 20180005704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/631263 [patent_app_country] => US [patent_app_date] => 2017-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8456 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15631263 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/631263
Semiconductor device having an anti-fuse element and method for suppressing the expansion of the cell current distribution to improve the writing yield thereof Jun 22, 2017 Issued
Array ( [id] => 15169507 [patent_doc_number] => 10490256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Layout of semiconductor memory device including sub wordline driver [patent_app_type] => utility [patent_app_number] => 15/631855 [patent_app_country] => US [patent_app_date] => 2017-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6675 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15631855 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/631855
Layout of semiconductor memory device including sub wordline driver Jun 22, 2017 Issued
Array ( [id] => 14858765 [patent_doc_number] => 10418116 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Memory device with control logic configured to group memory blocks, and determine driving voltages to be respectively applied to the groups to control memory operation [patent_app_type] => utility [patent_app_number] => 15/630667 [patent_app_country] => US [patent_app_date] => 2017-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 10021 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15630667 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/630667
Memory device with control logic configured to group memory blocks, and determine driving voltages to be respectively applied to the groups to control memory operation Jun 21, 2017 Issued
Array ( [id] => 13214295 [patent_doc_number] => 10121522 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-06 [patent_title] => Sense circuit with two sense nodes for cascade sensing [patent_app_type] => utility [patent_app_number] => 15/630089 [patent_app_country] => US [patent_app_date] => 2017-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 14415 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15630089 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/630089
Sense circuit with two sense nodes for cascade sensing Jun 21, 2017 Issued
Array ( [id] => 14737965 [patent_doc_number] => 10388391 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Memory device and operating method thereof using channel boosting before read or verify operation [patent_app_type] => utility [patent_app_number] => 15/617043 [patent_app_country] => US [patent_app_date] => 2017-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6515 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15617043 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/617043
Memory device and operating method thereof using channel boosting before read or verify operation Jun 7, 2017 Issued
Array ( [id] => 12095331 [patent_doc_number] => 20170352424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'Plural Distributed PBS with Both Voltage and Current Sensing SA for J-Page Hierarchical NAND Array\'s Concurrent Operations' [patent_app_type] => utility [patent_app_number] => 15/615883 [patent_app_country] => US [patent_app_date] => 2017-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9335 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15615883 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/615883
Plural Distributed PBS with Both Voltage and Current Sensing SA for J-Page Hierarchical NAND Array's Concurrent Operations Jun 6, 2017 Abandoned
Array ( [id] => 13597755 [patent_doc_number] => 20180350426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => PROMOTING UTILIZATION OF STORE BANDWIDTH OF A BANKED CACHE [patent_app_type] => utility [patent_app_number] => 15/615313 [patent_app_country] => US [patent_app_date] => 2017-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6539 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15615313 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/615313
Banked cache temporarily favoring selection of store requests from one of multiple store queues Jun 5, 2017 Issued
Array ( [id] => 12595116 [patent_doc_number] => 20180090202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => SEMICONDUCTOR MEMORY DEVICE, FLASH MEMORY AND CONTINUOUS READING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/614631 [patent_app_country] => US [patent_app_date] => 2017-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6457 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15614631 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/614631
NAND flash memory device performing continuous reading operation using NOR compatible command, address and control scheme Jun 5, 2017 Issued
Array ( [id] => 13754449 [patent_doc_number] => 10170176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Apparatus and methods for generating reference voltages for input buffers of a memory device [patent_app_type] => utility [patent_app_number] => 15/614677 [patent_app_country] => US [patent_app_date] => 2017-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 11668 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15614677 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/614677
Apparatus and methods for generating reference voltages for input buffers of a memory device Jun 5, 2017 Issued
Array ( [id] => 14366461 [patent_doc_number] => 10304542 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Memory device and method of operating the same to prevent occurrence of read fail by adjusting bit line voltage [patent_app_type] => utility [patent_app_number] => 15/613649 [patent_app_country] => US [patent_app_date] => 2017-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 10317 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15613649 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/613649
Memory device and method of operating the same to prevent occurrence of read fail by adjusting bit line voltage Jun 4, 2017 Issued
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