Search

Mushfique Siddique

Examiner (ID: 16359, Phone: (571)270-0424 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
838
Issued Applications
687
Pending Applications
93
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12235843 [patent_doc_number] => 20180068706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/613909 [patent_app_country] => US [patent_app_date] => 2017-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7134 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15613909 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/613909
Operational disturbance mitigation by controlling word line discharge when an external power supply voltage is reduced during operation of semiconductor memory device Jun 4, 2017 Issued
Array ( [id] => 13159271 [patent_doc_number] => 10096369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => Semiconductor device including a voltage generation circuit, and voltage generation circuit generates a required voltage according to internal data requested in response to an operation [patent_app_type] => utility [patent_app_number] => 15/611791 [patent_app_country] => US [patent_app_date] => 2017-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 5919 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15611791 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/611791
Semiconductor device including a voltage generation circuit, and voltage generation circuit generates a required voltage according to internal data requested in response to an operation Jun 1, 2017 Issued
Array ( [id] => 13708745 [patent_doc_number] => 20170365327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => Memory Devices Including Buffer Memory and Memory Modules Including the Same [patent_app_type] => utility [patent_app_number] => 15/611169 [patent_app_country] => US [patent_app_date] => 2017-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11938 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15611169 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/611169
Memory device using sense amplifiers as buffer memory with reduced access time and method of cache operation of the same May 31, 2017 Issued
Array ( [id] => 12054272 [patent_doc_number] => 20170330616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'DETERMINING A CELL STATE OF A RESISTIVE MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 15/605936 [patent_app_country] => US [patent_app_date] => 2017-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6394 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15605936 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/605936
Method and apparatus for determining a cell state of a resistive memory cell May 24, 2017 Issued
Array ( [id] => 13921115 [patent_doc_number] => 10204681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-12 [patent_title] => Control circuit configured to terminate a set operation and a reset operation of a resistive memory cell of memory array based on the voltage variation on the data line of the resistive memory cell [patent_app_type] => utility [patent_app_number] => 15/591085 [patent_app_country] => US [patent_app_date] => 2017-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6397 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15591085 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/591085
Control circuit configured to terminate a set operation and a reset operation of a resistive memory cell of memory array based on the voltage variation on the data line of the resistive memory cell May 8, 2017 Issued
Array ( [id] => 13558453 [patent_doc_number] => 20180330774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => REFRESH IN MEMORY BASED ON A SET MARGIN [patent_app_type] => utility [patent_app_number] => 15/590143 [patent_app_country] => US [patent_app_date] => 2017-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3949 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15590143 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/590143
Refresh in memory based on a set margin May 8, 2017 Issued
Array ( [id] => 15199857 [patent_doc_number] => 10497430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on power supply voltage detection circuits [patent_app_type] => utility [patent_app_number] => 15/587911 [patent_app_country] => US [patent_app_date] => 2017-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 33 [patent_no_of_words] => 17243 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15587911 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/587911
Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on power supply voltage detection circuits May 4, 2017 Issued
Array ( [id] => 12758863 [patent_doc_number] => 20180144789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM INCLUDING THE SAME AND READ AND WRITE OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/584591 [patent_app_country] => US [patent_app_date] => 2017-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4720 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15584591 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/584591
Memory device with separate read active signal and write active signal having different activation periods used for word line selection during read and write operation May 1, 2017 Issued
Array ( [id] => 14800715 [patent_doc_number] => 10403366 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-09-03 [patent_title] => Method and system for adapting solid state memory write parameters to satisfy performance goals based on degree of read errors [patent_app_type] => utility [patent_app_number] => 15/581285 [patent_app_country] => US [patent_app_date] => 2017-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6884 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15581285 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/581285
Method and system for adapting solid state memory write parameters to satisfy performance goals based on degree of read errors Apr 27, 2017 Issued
Array ( [id] => 13819067 [patent_doc_number] => 10186306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-22 [patent_title] => Apparatus and method for non-volatile memory address decoding [patent_app_type] => utility [patent_app_number] => 15/489983 [patent_app_country] => US [patent_app_date] => 2017-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4152 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15489983 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/489983
Apparatus and method for non-volatile memory address decoding Apr 17, 2017 Issued
Array ( [id] => 14332591 [patent_doc_number] => 10297319 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Memory device with unipolar resistive memory cells with programmable resistive element end control transistor and set/reset operations of thereof [patent_app_type] => utility [patent_app_number] => 15/487303 [patent_app_country] => US [patent_app_date] => 2017-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5009 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 324 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15487303 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/487303
Memory device with unipolar resistive memory cells with programmable resistive element end control transistor and set/reset operations of thereof Apr 12, 2017 Issued
Array ( [id] => 12162299 [patent_doc_number] => 20180033564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-01 [patent_title] => 'MICROELECTROMECHANICAL DEVICE, WHICH CAN BE USED AS NON-VOLATILE MEMORY MODULE OR RELAY, AND MEMORY INCLUDING A PLURALITY OF MICROELECTROMECHANICAL DEVICES' [patent_app_type] => utility [patent_app_number] => 15/470431 [patent_app_country] => US [patent_app_date] => 2017-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6629 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15470431 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/470431
Microelectromechanical device, which can be used as non-volatile memory module or relay, and memory including a plurality of microelectromechanical devices Mar 26, 2017 Issued
Array ( [id] => 16233675 [patent_doc_number] => 10741235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-11 [patent_title] => Refresh address controlling scheme based on refresh counter and mask circuit [patent_app_type] => utility [patent_app_number] => 15/436249 [patent_app_country] => US [patent_app_date] => 2017-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 5072 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15436249 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/436249
Refresh address controlling scheme based on refresh counter and mask circuit Feb 16, 2017 Issued
Array ( [id] => 11665944 [patent_doc_number] => 20170154664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'Compact System with Memory and PMU Integration' [patent_app_type] => utility [patent_app_number] => 15/430747 [patent_app_country] => US [patent_app_date] => 2017-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5053 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15430747 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/430747
Compact system with memory and PMU integration Feb 12, 2017 Issued
Array ( [id] => 12026584 [patent_doc_number] => 20170316683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'Modular Sensor Systems' [patent_app_type] => utility [patent_app_number] => 15/431584 [patent_app_country] => US [patent_app_date] => 2017-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 55 [patent_no_of_words] => 11536 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15431584 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/431584
Modular Sensor Systems Feb 12, 2017 Abandoned
Array ( [id] => 13005595 [patent_doc_number] => 10026468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => DRAM with segmented word line switching circuit for causing selection of portion of rows and circuitry for a variable page width control scheme [patent_app_type] => utility [patent_app_number] => 15/430393 [patent_app_country] => US [patent_app_date] => 2017-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2898 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15430393 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/430393
DRAM with segmented word line switching circuit for causing selection of portion of rows and circuitry for a variable page width control scheme Feb 9, 2017 Issued
Array ( [id] => 11630629 [patent_doc_number] => 20170140818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'VARIABLE RESISTANCE MEMORY DEVICE AND VERIFY METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/421497 [patent_app_country] => US [patent_app_date] => 2017-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5849 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15421497 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/421497
VARIABLE RESISTANCE MEMORY DEVICE AND VERIFY METHOD THEREOF Jan 31, 2017 Abandoned
Array ( [id] => 13334457 [patent_doc_number] => 20180218766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => Method for low power operation and test using DRAM device [patent_app_type] => utility [patent_app_number] => 15/420679 [patent_app_country] => US [patent_app_date] => 2017-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6258 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15420679 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/420679
Method for low power operation and test using DRAM device Jan 30, 2017 Issued
Array ( [id] => 11854671 [patent_doc_number] => 20170229163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-10 [patent_title] => 'Magnetic Memory' [patent_app_type] => utility [patent_app_number] => 15/421117 [patent_app_country] => US [patent_app_date] => 2017-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6571 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15421117 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/421117
Apparatus and method for controlling write current of magnetic memory based on temperature dependent coercive force Jan 30, 2017 Issued
Array ( [id] => 15014731 [patent_doc_number] => 10453521 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => Layout of semiconductor device for selectively operating as insulating circuit or driving circuit [patent_app_type] => utility [patent_app_number] => 15/417807 [patent_app_country] => US [patent_app_date] => 2017-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 12446 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15417807 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/417807
Layout of semiconductor device for selectively operating as insulating circuit or driving circuit Jan 26, 2017 Issued
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