Mushfique Siddique

Array ( [id] => 13321215 [patent_doc_number] => 20180212145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => LOW-VOLTAGE THRESHOLD SWITCH DEVICES WITH CURRENT-CONTROLLED NEGATIVE DIFFERENTIAL RESISTANCE BASED ON ELECTROFORMED VANADIUM OXIDE LAYER [patent_app_type] => utility [patent_app_number] => 15/417049 [patent_app_country] => US [patent_app_date] => 2017-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8438 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15417049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11622879 [patent_doc_number] => 20170133067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'INPUT CIRCUIT OF THREE-DIMENSIONAL SEMICONDUCTOR APPARATUS CAPABLE OF ENABLING TESTING AND DIRECT ACCESS' [patent_app_type] => utility [patent_app_number] => 15/416130 [patent_app_country] => US [patent_app_date] => 2017-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3676 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15416130 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11746810 [patent_doc_number] => 20170200883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-13 [patent_title] => 'ELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/416918 [patent_app_country] => US [patent_app_date] => 2017-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11754 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15416918 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11959161 [patent_doc_number] => 20170263313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/415788 [patent_app_country] => US [patent_app_date] => 2017-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9533 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15415788 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12202243 [patent_doc_number] => 09905315 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-27 [patent_title] => 'Error-resilient memory device with row and/or column folding with redundant resources and repair method thereof' [patent_app_type] => utility [patent_app_number] => 15/413429 [patent_app_country] => US [patent_app_date] => 2017-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7998 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15413429 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14332605 [patent_doc_number] => 10297326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Sense amplifier and latch circuit for a semiconductor memory device and method of operation thereof [patent_app_type] => utility [patent_app_number] => 15/411225 [patent_app_country] => US [patent_app_date] => 2017-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 21775 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15411225 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13666599 [patent_doc_number] => 10163470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Dual rail memory, memory macro and associated hybrid power supply method [patent_app_type] => utility [patent_app_number] => 15/380543 [patent_app_country] => US [patent_app_date] => 2016-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6385 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15380543 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13740093 [patent_doc_number] => 20180374516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => SEMICONDUCTOR STORAGE DEVICE AND METHOD OF CONTROLLING SEMICONDUCTOR STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 16/064617 [patent_app_country] => US [patent_app_date] => 2016-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14174 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16064617 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11437964 [patent_doc_number] => 20170038985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-09 [patent_title] => 'NONVOLATILE MEMORY DATA RECOVERY AFTER POWER FAILURE' [patent_app_type] => utility [patent_app_number] => 15/298636 [patent_app_country] => US [patent_app_date] => 2016-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8013 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15298636 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12534204 [patent_doc_number] => 10008258 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-26 [patent_title] => Method and circuit to enable wide supply voltage difference in multi-supply memory [patent_app_type] => utility [patent_app_number] => 15/296567 [patent_app_country] => US [patent_app_date] => 2016-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 7239 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15296567 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14721913 [patent_doc_number] => 20190252020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => TWO TRANSISTOR, ONE RESISTOR NON-VOLATILE GAIN CELL MEMORY AND STORAGE ELEMENT [patent_app_type] => utility [patent_app_number] => 16/320023 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7150 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16320023 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14721913 [patent_doc_number] => 20190252020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => TWO TRANSISTOR, ONE RESISTOR NON-VOLATILE GAIN CELL MEMORY AND STORAGE ELEMENT [patent_app_type] => utility [patent_app_number] => 16/320023 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7150 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16320023 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11517750 [patent_doc_number] => 20170084825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'MAGNETIC TUNNEL JUNCTION DEVICE AND SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/265970 [patent_app_country] => US [patent_app_date] => 2016-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13117 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15265970 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11952161 [patent_doc_number] => 20170256312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/265067 [patent_app_country] => US [patent_app_date] => 2016-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7720 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15265067 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12416292 [patent_doc_number] => 09972377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-15 [patent_title] => Refresh controller and memory device including the same [patent_app_type] => utility [patent_app_number] => 15/262183 [patent_app_country] => US [patent_app_date] => 2016-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8396 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15262183 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11959173 [patent_doc_number] => 20170263325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/261487 [patent_app_country] => US [patent_app_date] => 2016-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12636 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15261487 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12968653 [patent_doc_number] => 09875785 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-23 [patent_title] => Refresh timer synchronization between memory controller and memory [patent_app_type] => utility [patent_app_number] => 15/246371 [patent_app_country] => US [patent_app_date] => 2016-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2863 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15246371 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12005166 [patent_doc_number] => 20170309321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-26 [patent_title] => 'Peak Current Bypass Protection Control Device Applicable in MRAM' [patent_app_type] => utility [patent_app_number] => 15/239013 [patent_app_country] => US [patent_app_date] => 2016-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4151 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15239013 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12181441 [patent_doc_number] => 20180040377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'MULTI-DECK MEMORY DEVICE AND OPERATIONS' [patent_app_type] => utility [patent_app_number] => 15/231011 [patent_app_country] => US [patent_app_date] => 2016-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 15611 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15231011 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12174626 [patent_doc_number] => 09892772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-13 [patent_title] => 'Semiconductor system and method of performing write leveling operation thereof' [patent_app_type] => utility [patent_app_number] => 15/225961 [patent_app_country] => US [patent_app_date] => 2016-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6550 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15225961 [rel_patent_id] =>[rel_patent_doc_number] =>)