| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 11517258
[patent_doc_number] => 20170084332
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-23
[patent_title] => 'POWER SUPPLY CIRCUITS WITH VARIABLE NUMBER OF POWER INPUTS AND STORAGE DEVICES HAVING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 15/196473
[patent_app_country] => US
[patent_app_date] => 2016-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 12611
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15196473
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/196473 | Power supply circuits with variable number of power inputs and cross-coupled diodes and storage devices having the same | Jun 28, 2016 | Issued |
Array
(
[id] => 12953020
[patent_doc_number] => 09837146
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-12-05
[patent_title] => Memory system temperature management
[patent_app_type] => utility
[patent_app_number] => 15/195927
[patent_app_country] => US
[patent_app_date] => 2016-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 13585
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 315
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15195927
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/195927 | Memory system temperature management | Jun 27, 2016 | Issued |
Array
(
[id] => 13723647
[patent_doc_number] => 20170372779
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-28
[patent_title] => OTS FOR NVM ARRAY SELECT LINES
[patent_app_type] => utility
[patent_app_number] => 15/194675
[patent_app_country] => US
[patent_app_date] => 2016-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5472
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15194675
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/194675 | Ovonic threshold switch (OTS) driver/selector uses unselect bias to pre-charge memory chip circuit and reduces unacceptable false selects | Jun 27, 2016 | Issued |
Array
(
[id] => 12968623
[patent_doc_number] => 09875775
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-01-23
[patent_title] => Sense amplifier and input/output circuit of semiconductor apparatus including the same
[patent_app_type] => utility
[patent_app_number] => 15/193287
[patent_app_country] => US
[patent_app_date] => 2016-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3625
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15193287
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/193287 | Sense amplifier and input/output circuit of semiconductor apparatus including the same | Jun 26, 2016 | Issued |
Array
(
[id] => 12019501
[patent_doc_number] => 09812210
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-11-07
[patent_title] => 'Power off period estimating method for solid state storage device'
[patent_app_type] => utility
[patent_app_number] => 15/191701
[patent_app_country] => US
[patent_app_date] => 2016-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 4898
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 234
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15191701
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/191701 | Power off period estimating method for solid state storage device | Jun 23, 2016 | Issued |
Array
(
[id] => 13131597
[patent_doc_number] => 10083736
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-09-25
[patent_title] => Adaptive calibration scheduling for a memory subsystem based on calibrations of delay applied to data strobe and calibration of reference voltage
[patent_app_type] => utility
[patent_app_number] => 15/190291
[patent_app_country] => US
[patent_app_date] => 2016-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 7321
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15190291
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/190291 | Adaptive calibration scheduling for a memory subsystem based on calibrations of delay applied to data strobe and calibration of reference voltage | Jun 22, 2016 | Issued |
Array
(
[id] => 13708753
[patent_doc_number] => 20170365331
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-21
[patent_title] => Boost Circuit for Memory
[patent_app_type] => utility
[patent_app_number] => 15/188873
[patent_app_country] => US
[patent_app_date] => 2016-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4985
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15188873
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/188873 | Boost circuit for memory | Jun 20, 2016 | Issued |
Array
(
[id] => 12101902
[patent_doc_number] => 09859000
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-01-02
[patent_title] => 'Apparatus for providing adjustable reference voltage for sensing read-out data for memory'
[patent_app_type] => utility
[patent_app_number] => 15/185037
[patent_app_country] => US
[patent_app_date] => 2016-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 4639
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 327
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15185037
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/185037 | Apparatus for providing adjustable reference voltage for sensing read-out data for memory | Jun 16, 2016 | Issued |
Array
(
[id] => 13708811
[patent_doc_number] => 20170365360
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-21
[patent_title] => PLATE DEFECT MITIGATION TECHNIQUES
[patent_app_type] => utility
[patent_app_number] => 15/184795
[patent_app_country] => US
[patent_app_date] => 2016-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 21017
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15184795
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/184795 | Plate defect mitigation techniques | Jun 15, 2016 | Issued |
Array
(
[id] => 12477186
[patent_doc_number] => 09990981
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-06-05
[patent_title] => Synchronous dynamic random access memory (SDRAM) and memory controller device mounted in single system in package (SIP)
[patent_app_type] => utility
[patent_app_number] => 15/178091
[patent_app_country] => US
[patent_app_date] => 2016-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 20
[patent_no_of_words] => 9531
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 302
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15178091
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/178091 | Synchronous dynamic random access memory (SDRAM) and memory controller device mounted in single system in package (SIP) | Jun 8, 2016 | Issued |
Array
(
[id] => 12040224
[patent_doc_number] => 09818460
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-11-14
[patent_title] => 'Negative bitline write assist circuit and method for operating the same'
[patent_app_type] => utility
[patent_app_number] => 15/162477
[patent_app_country] => US
[patent_app_date] => 2016-05-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 5967
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15162477
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/162477 | Negative bitline write assist circuit and method for operating the same | May 22, 2016 | Issued |
Array
(
[id] => 12570762
[patent_doc_number] => 10019170
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-07-10
[patent_title] => Controlling timing and edge transition of a delayed clock signal and data latching methods using such a delayed clock signal
[patent_app_type] => utility
[patent_app_number] => 15/084979
[patent_app_country] => US
[patent_app_date] => 2016-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 9631
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15084979
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/084979 | Controlling timing and edge transition of a delayed clock signal and data latching methods using such a delayed clock signal | Mar 29, 2016 | Issued |
Array
(
[id] => 11959155
[patent_doc_number] => 20170263306
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-09-14
[patent_title] => 'APPARATUSES AND METHODS FOR LOGIC/MEMORY DEVICES'
[patent_app_type] => utility
[patent_app_number] => 15/066831
[patent_app_country] => US
[patent_app_date] => 2016-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 14152
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15066831
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/066831 | Processing in memory (PIM) capable memory device having sensing circuitry performing logic operations | Mar 9, 2016 | Issued |
Array
(
[id] => 11653077
[patent_doc_number] => 20170148978
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-25
[patent_title] => 'CROSS-POINT ARCHITECTURE FOR SPIN-TRANSFER TORQUE MAGNETORESISTIVE RANDOM ACCESS MEMORY WITH SPIN ORBIT WRITING'
[patent_app_type] => utility
[patent_app_number] => 15/067087
[patent_app_country] => US
[patent_app_date] => 2016-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 9037
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15067087
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/067087 | Cross-point architecture for spin-transfer torque magnetoresistive random access memory with spin orbit writing | Mar 9, 2016 | Issued |
Array
(
[id] => 13159265
[patent_doc_number] => 10096366
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-10-09
[patent_title] => Memory system including multi-plane flash memory and controller
[patent_app_type] => utility
[patent_app_number] => 15/066255
[patent_app_country] => US
[patent_app_date] => 2016-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 37
[patent_figures_cnt] => 43
[patent_no_of_words] => 19199
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15066255
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/066255 | Memory system including multi-plane flash memory and controller | Mar 9, 2016 | Issued |
Array
(
[id] => 13159245
[patent_doc_number] => 10096356
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-10-09
[patent_title] => Method of operation of non-volatile memory device
[patent_app_type] => utility
[patent_app_number] => 15/065351
[patent_app_country] => US
[patent_app_date] => 2016-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 10149
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15065351
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/065351 | Method of operation of non-volatile memory device | Mar 8, 2016 | Issued |
Array
(
[id] => 11096284
[patent_doc_number] => 20160293253
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-10-06
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/065341
[patent_app_country] => US
[patent_app_date] => 2016-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 39
[patent_figures_cnt] => 39
[patent_no_of_words] => 16532
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15065341
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/065341 | Semiconductor memory device including variable resistance element | Mar 8, 2016 | Issued |
Array
(
[id] => 11475251
[patent_doc_number] => 20170062033
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-02
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/065449
[patent_app_country] => US
[patent_app_date] => 2016-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 10732
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15065449
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/065449 | Semiconductor memory device for sensing memory cell with variable resistance | Mar 8, 2016 | Issued |
Array
(
[id] => 11952169
[patent_doc_number] => 20170256320
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-09-07
[patent_title] => 'Adaptive Determination Of Program Parameter Using Program Of Erase Rate'
[patent_app_type] => utility
[patent_app_number] => 15/062661
[patent_app_country] => US
[patent_app_date] => 2016-03-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 36
[patent_figures_cnt] => 36
[patent_no_of_words] => 24324
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15062661
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/062661 | Adaptive determination of program parameter using program of erase rate | Mar 6, 2016 | Issued |
Array
(
[id] => 11495195
[patent_doc_number] => 20170069380
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-03-09
[patent_title] => 'MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 15/062093
[patent_app_country] => US
[patent_app_date] => 2016-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 8900
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15062093
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/062093 | MEMORY DEVICE | Mar 4, 2016 | Abandoned |