Mushfique Siddique

Array ( [id] => 11952141 [patent_doc_number] => 20170256292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-07 [patent_title] => 'MEMORY ARRAY POWER REDUCTION THROUGH REDUCED SUPPLY VOLTAGE' [patent_app_type] => utility [patent_app_number] => 15/058631 [patent_app_country] => US [patent_app_date] => 2016-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7307 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15058631 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11890722 [patent_doc_number] => 09761285 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-12 [patent_title] => 'Sense amplifier and latching scheme' [patent_app_type] => utility [patent_app_number] => 15/054553 [patent_app_country] => US [patent_app_date] => 2016-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3394 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15054553 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11939499 [patent_doc_number] => 20170243649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'NONVOLATILE MEMORY CELL EMPLOYING HOT CARRIER EFFECT FOR DATA STORAGE' [patent_app_type] => utility [patent_app_number] => 15/047759 [patent_app_country] => US [patent_app_date] => 2016-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7460 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15047759 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11108828 [patent_doc_number] => 20160305797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-20 [patent_title] => 'Modular System Including Multiple Detachable Sensors' [patent_app_type] => utility [patent_app_number] => 15/043553 [patent_app_country] => US [patent_app_date] => 2016-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6571 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15043553 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12256772 [patent_doc_number] => 09928921 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-27 [patent_title] => 'Non-volatile memory, semiconductor device and reading method' [patent_app_type] => utility [patent_app_number] => 15/042730 [patent_app_country] => US [patent_app_date] => 2016-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10560 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15042730 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11532385 [patent_doc_number] => 20170092363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE INCLUDING THREE-DIMENSIONAL ARRAY STRUCTURE AND MEMORY SYSTEM INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/040099 [patent_app_country] => US [patent_app_date] => 2016-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11096 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15040099 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11028863 [patent_doc_number] => 20160225819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'MAGNETIC MEMORY CELLS WITH HIGH WRITE CURRENT AND READ STABILITY' [patent_app_type] => utility [patent_app_number] => 15/012813 [patent_app_country] => US [patent_app_date] => 2016-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 10239 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15012813 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12214681 [patent_doc_number] => 09911496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-06 [patent_title] => 'Associative memory for realizing a k-nearest neighbors algorithm' [patent_app_type] => utility [patent_app_number] => 15/009699 [patent_app_country] => US [patent_app_date] => 2016-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9220 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 452 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15009699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16293287 [patent_doc_number] => 10770140 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Memristive array with parallel reset control devices [patent_app_type] => utility [patent_app_number] => 16/065771 [patent_app_country] => US [patent_app_date] => 2016-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8218 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16065771 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14011221 [patent_doc_number] => 10224085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-05 [patent_title] => Magnetic memory cell with asymmetrical geometry programmable by application of current in the absence of a magnetic field [patent_app_type] => utility [patent_app_number] => 15/540159 [patent_app_country] => US [patent_app_date] => 2016-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 17 [patent_no_of_words] => 3722 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15540159 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14706595 [patent_doc_number] => 10381055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Flexible DLL (delay locked loop) calibration [patent_app_type] => utility [patent_app_number] => 14/998185 [patent_app_country] => US [patent_app_date] => 2015-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11752 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14998185 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10808562 [patent_doc_number] => 20160154720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-02 [patent_title] => 'PRESSURE TESTING METHOD AND PRESSURE TESTING DEVICE FOR A QUICK PATH INTERCONNECT BUS' [patent_app_type] => utility [patent_app_number] => 14/952358 [patent_app_country] => US [patent_app_date] => 2015-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3153 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14952358 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11628614 [patent_doc_number] => 20170138803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'VISUALIZATION AND MANIPULATION OF MICRO-SCALE CALORIMETER CHAMBER DATA MATRICES' [patent_app_type] => utility [patent_app_number] => 14/939686 [patent_app_country] => US [patent_app_date] => 2015-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8905 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14939686 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11592646 [patent_doc_number] => 20170117058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'NON-VOLATILE MEMORY CELL HAVING MULRTIPLE SIGNAL PATHWAYS TO PROVIDE ACCESS TO AN ANTIFUSE OF THE MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 14/925543 [patent_app_country] => US [patent_app_date] => 2015-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4806 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14925543 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11517242 [patent_doc_number] => 20170084317 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'DUAL RAIL MEMORY, MEMORY MACRO AND ASSOCIATED HYBRID POWER SUPPLY METHOD' [patent_app_type] => utility [patent_app_number] => 14/924069 [patent_app_country] => US [patent_app_date] => 2015-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5934 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14924069 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12375102 [patent_doc_number] => 09959926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-01 [patent_title] => Method and apparatus for selective write assist using shared boost capacitor [patent_app_type] => utility [patent_app_number] => 14/919533 [patent_app_country] => US [patent_app_date] => 2015-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5497 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14919533 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11132133 [patent_doc_number] => 20160329108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-10 [patent_title] => 'SEMICONDUCTOR MEMORY APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/883281 [patent_app_country] => US [patent_app_date] => 2015-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6278 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14883281 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10802529 [patent_doc_number] => 20160148686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'MEMORY CELL ARRAY OF RESISTIVE RANDOM-ACCESS MEMORIES' [patent_app_type] => utility [patent_app_number] => 14/877239 [patent_app_country] => US [patent_app_date] => 2015-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9602 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14877239 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10745752 [patent_doc_number] => 20160091903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'SAFETY AND PROGRAMMABLE LOGIC INTEGRATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/869672 [patent_app_country] => US [patent_app_date] => 2015-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 13126 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14869672 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16031575 [patent_doc_number] => 10678204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-09 [patent_title] => Universal analog cell for connecting the inputs and outputs of devices [patent_app_type] => utility [patent_app_number] => 14/869808 [patent_app_country] => US [patent_app_date] => 2015-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 5454 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14869808 [rel_patent_id] =>[rel_patent_doc_number] =>)