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Mushfique Siddique

Examiner (ID: 16359, Phone: (571)270-0424 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
838
Issued Applications
687
Pending Applications
93
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11854679 [patent_doc_number] => 20170229171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-10 [patent_title] => 'MEMORY ARRAY DRIVER' [patent_app_type] => utility [patent_app_number] => 15/328269 [patent_app_country] => US [patent_app_date] => 2014-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4488 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15328269 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/328269
Memory array driver Nov 3, 2014 Issued
Array ( [id] => 11811352 [patent_doc_number] => 09715925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-25 [patent_title] => 'Methods and apparatus for vertical cross point re-RAM array bias calibration' [patent_app_type] => utility [patent_app_number] => 14/502093 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 14072 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14502093 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/502093
Methods and apparatus for vertical cross point re-RAM array bias calibration Sep 29, 2014 Issued
Array ( [id] => 11811352 [patent_doc_number] => 09715925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-25 [patent_title] => 'Methods and apparatus for vertical cross point re-RAM array bias calibration' [patent_app_type] => utility [patent_app_number] => 14/502093 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 14072 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14502093 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/502093
Methods and apparatus for vertical cross point re-RAM array bias calibration Sep 29, 2014 Issued
Array ( [id] => 11811352 [patent_doc_number] => 09715925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-25 [patent_title] => 'Methods and apparatus for vertical cross point re-RAM array bias calibration' [patent_app_type] => utility [patent_app_number] => 14/502093 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 14072 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14502093 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/502093
Methods and apparatus for vertical cross point re-RAM array bias calibration Sep 29, 2014 Issued
Array ( [id] => 10747199 [patent_doc_number] => 20160093350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'LATCH OFFSET CANCELATION SENSE AMPLIFIER' [patent_app_type] => utility [patent_app_number] => 14/499153 [patent_app_country] => US [patent_app_date] => 2014-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7451 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14499153 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/499153
Latch offset cancelation for magnetoresistive random access memory Sep 26, 2014 Issued
Array ( [id] => 10740520 [patent_doc_number] => 20160086671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-24 [patent_title] => 'Utilizing NAND Strings in Dummy Blocks for Faster Bit Line Precharge' [patent_app_type] => utility [patent_app_number] => 14/495283 [patent_app_country] => US [patent_app_date] => 2014-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6836 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14495283 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/495283
Utilizing NAND strings in dummy blocks for faster bit line precharge Sep 23, 2014 Issued
Array ( [id] => 12256774 [patent_doc_number] => 09928923 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-27 [patent_title] => 'Estimation of level-thresholds for memory cells' [patent_app_type] => utility [patent_app_number] => 14/489983 [patent_app_country] => US [patent_app_date] => 2014-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7664 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14489983 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/489983
Estimation of level-thresholds for memory cells Sep 17, 2014 Issued
Array ( [id] => 11483110 [patent_doc_number] => 09589662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Resistive memory device with variable cell current amplification' [patent_app_type] => utility [patent_app_number] => 14/486441 [patent_app_country] => US [patent_app_date] => 2014-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4294 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14486441 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/486441
Resistive memory device with variable cell current amplification Sep 14, 2014 Issued
Array ( [id] => 10732810 [patent_doc_number] => 20160078960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'METHOD AND APPARATUS FOR WRITING DATA TO NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/485097 [patent_app_country] => US [patent_app_date] => 2014-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10214 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14485097 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/485097
METHOD AND APPARATUS FOR WRITING DATA TO NON-VOLATILE MEMORY Sep 11, 2014 Abandoned
Array ( [id] => 11252795 [patent_doc_number] => 09478307 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-25 [patent_title] => 'Memory device, writing method, and reading method' [patent_app_type] => utility [patent_app_number] => 14/483669 [patent_app_country] => US [patent_app_date] => 2014-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 41 [patent_no_of_words] => 19868 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14483669 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/483669
Memory device, writing method, and reading method Sep 10, 2014 Issued
Array ( [id] => 10370157 [patent_doc_number] => 20150255162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-10 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DETECTING LEAK CURRENT' [patent_app_type] => utility [patent_app_number] => 14/482641 [patent_app_country] => US [patent_app_date] => 2014-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9138 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14482641 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/482641
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DETECTING LEAK CURRENT Sep 9, 2014 Abandoned
Array ( [id] => 10328863 [patent_doc_number] => 20150213867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'MULTI-LEVEL CELL DESIGNS FOR HIGH DENSITY LOW POWER GSHE-STT MRAM' [patent_app_type] => utility [patent_app_number] => 14/479539 [patent_app_country] => US [patent_app_date] => 2014-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6437 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14479539 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/479539
MULTI-LEVEL CELL DESIGNS FOR HIGH DENSITY LOW POWER GSHE-STT MRAM Sep 7, 2014 Abandoned
Array ( [id] => 11644920 [patent_doc_number] => 09666309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-30 [patent_title] => 'Method and device for repairing memory' [patent_app_type] => utility [patent_app_number] => 14/479657 [patent_app_country] => US [patent_app_date] => 2014-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 4767 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14479657 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/479657
Method and device for repairing memory Sep 7, 2014 Issued
Array ( [id] => 9929877 [patent_doc_number] => 20150078069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-19 [patent_title] => 'INTEGRATED CMOS CIRCUIT HAVING FIRST AND SECOND CIRCUIT PARTS' [patent_app_type] => utility [patent_app_number] => 14/478477 [patent_app_country] => US [patent_app_date] => 2014-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3698 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14478477 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/478477
Integrated CMOS circuit having first and second circuit parts Sep 4, 2014 Issued
Array ( [id] => 10261493 [patent_doc_number] => 20150146489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'METHOD OF OPERATING NONVOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/477513 [patent_app_country] => US [patent_app_date] => 2014-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 20333 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14477513 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/477513
METHOD OF OPERATING NONVOLATILE MEMORY DEVICE Sep 3, 2014 Abandoned
Array ( [id] => 10447769 [patent_doc_number] => 20150332783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-19 [patent_title] => 'METHOD OF OPERATING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/475187 [patent_app_country] => US [patent_app_date] => 2014-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5963 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14475187 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/475187
METHOD OF OPERATING SEMICONDUCTOR DEVICE Sep 1, 2014 Abandoned
Array ( [id] => 14425345 [patent_doc_number] => 10317472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Power storage system for predicting abnormality or failure of the system by using multivariate analysis [patent_app_type] => utility [patent_app_number] => 14/917713 [patent_app_country] => US [patent_app_date] => 2014-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9853 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 512 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14917713 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/917713
Power storage system for predicting abnormality or failure of the system by using multivariate analysis Aug 21, 2014 Issued
Array ( [id] => 10702608 [patent_doc_number] => 20160048755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'FLOATING-GATE TRANSISTOR ARRAY FOR PERFORMING WEIGHTED SUM COMPUTATION' [patent_app_type] => utility [patent_app_number] => 14/459577 [patent_app_country] => US [patent_app_date] => 2014-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6573 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14459577 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/459577
Floating-gate transistor array for performing weighted sum computation Aug 13, 2014 Issued
Array ( [id] => 10696649 [patent_doc_number] => 20160042796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-11 [patent_title] => 'LOW LATENCY MEMORY ERASE SUSPEND OPERATION' [patent_app_type] => utility [patent_app_number] => 14/455749 [patent_app_country] => US [patent_app_date] => 2014-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6212 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14455749 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/455749
Low latency memory erase suspend operation Aug 7, 2014 Issued
Array ( [id] => 10689288 [patent_doc_number] => 20160035433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'MEMORY ARRAY WITH RAM AND EMBEDDED ROM' [patent_app_type] => utility [patent_app_number] => 14/447515 [patent_app_country] => US [patent_app_date] => 2014-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9648 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14447515 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/447515
Memory array with RAM and embedded ROM Jul 29, 2014 Issued
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