Mushfique Siddique

Array ( [id] => 19237046 [patent_doc_number] => 20240194241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => DEVICE AND METHOD FOR CALIBRATING REFERENCE VOLTAGE [patent_app_type] => utility [patent_app_number] => 18/223097 [patent_app_country] => US [patent_app_date] => 2023-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3592 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18223097 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20189584 [patent_doc_number] => 12400706 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => In memory searching device [patent_app_type] => utility [patent_app_number] => 18/347571 [patent_app_country] => US [patent_app_date] => 2023-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 0 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18347571 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19356701 [patent_doc_number] => 12057156 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Quadrature error correction circuit and semiconductor memory device including the same [patent_app_type] => utility [patent_app_number] => 18/218243 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 32 [patent_no_of_words] => 16141 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18218243 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18743092 [patent_doc_number] => 20230352080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => SENSE AMPLIFIER WITH DIGIT LINE MULTIPLEXING [patent_app_type] => utility [patent_app_number] => 18/217205 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18439 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18217205 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18848486 [patent_doc_number] => 20230410890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => Memory System Topologies Including A Memory Die Stack [patent_app_type] => utility [patent_app_number] => 18/340726 [patent_app_country] => US [patent_app_date] => 2023-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26450 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18340726 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18714774 [patent_doc_number] => 20230337418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => MEMORY CORE CIRCUIT HAVING CELL ON PERIPHERY STRUCTURE AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/211807 [patent_app_country] => US [patent_app_date] => 2023-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14938 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18211807 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19733587 [patent_doc_number] => 12211587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => SRAM with tracking circuitry for reducing active power [patent_app_type] => utility [patent_app_number] => 18/336418 [patent_app_country] => US [patent_app_date] => 2023-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 11949 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18336418 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19646241 [patent_doc_number] => 20240420761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => ENDURANCE, POWER, AND PERFORMANCE IMPROVEMENT LOGIC FOR A MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 18/333916 [patent_app_country] => US [patent_app_date] => 2023-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8388 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18333916 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19634344 [patent_doc_number] => 20240412793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => NON-VOLATILE MEMORY AND PROGRAMMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/329583 [patent_app_country] => US [patent_app_date] => 2023-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3696 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18329583 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19679068 [patent_doc_number] => 12190939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Memory subword driver circuits and layout [patent_app_type] => utility [patent_app_number] => 18/313948 [patent_app_country] => US [patent_app_date] => 2023-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 11947 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18313948 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20215955 [patent_doc_number] => 12412609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Method of reducing program disturbance in memory device and memory device utilizing same [patent_app_type] => utility [patent_app_number] => 18/139316 [patent_app_country] => US [patent_app_date] => 2023-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 3736 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18139316 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19260674 [patent_doc_number] => 12020739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-25 [patent_title] => Memory device for reducing row hammer disturbance, and a method of refreshing the same [patent_app_type] => utility [patent_app_number] => 18/138849 [patent_app_country] => US [patent_app_date] => 2023-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9076 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18138849 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19531477 [patent_doc_number] => 20240355379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => Voltage Range for Training Physical Memory [patent_app_type] => utility [patent_app_number] => 18/305080 [patent_app_country] => US [patent_app_date] => 2023-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5360 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18305080 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18812227 [patent_doc_number] => 20230386564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => ENHANCED ACCURACY OF BIT LINE READING FOR AN IN-MEMORY COMPUTE OPERATION BY ACCOUNTING FOR VARIATION IN READ CURRENT [patent_app_type] => utility [patent_app_number] => 18/137159 [patent_app_country] => US [patent_app_date] => 2023-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9198 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18137159 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18848488 [patent_doc_number] => 20230410892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => BIT LINE READ CURRENT MIRRORING CIRCUIT FOR AN IN-MEMORY COMPUTE OPERATION WHERE SIMULTANEOUS ACCESS IS MADE TO PLURAL ROWS OF A STATIC RANDOM ACCESS MEMORY (SRAM) [patent_app_type] => utility [patent_app_number] => 18/137261 [patent_app_country] => US [patent_app_date] => 2023-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18137261 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20332583 [patent_doc_number] => 12462867 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Memory devices having sense amplifiers therein that support offset cancellation having improved sense amplifier characteristics and methods of operating same [patent_app_type] => utility [patent_app_number] => 18/303522 [patent_app_country] => US [patent_app_date] => 2023-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3665 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18303522 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19168253 [patent_doc_number] => 11984164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Non-volatile static random access memory (nvSRAM) with multiple magnetic tunnel junction cells [patent_app_type] => utility [patent_app_number] => 18/300706 [patent_app_country] => US [patent_app_date] => 2023-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9949 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18300706 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18712550 [patent_doc_number] => 20230335183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => SEMICONDUCTOR-ELEMENT-INCLUDING MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/299363 [patent_app_country] => US [patent_app_date] => 2023-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11570 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 462 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18299363 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20118197 [patent_doc_number] => 12367912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Semiconductor storage device including sense amplifier that senses data from multiple memory circuits [patent_app_type] => utility [patent_app_number] => 18/184329 [patent_app_country] => US [patent_app_date] => 2023-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 2311 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18184329 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18488141 [patent_doc_number] => 20230215489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => MEMORY DEVICE ARCHITECTURE USING MULTIPLE PHYSICAL CELLS PER BIT TO IMPROVE READ MARGIN AND TO ALLEVIATE THE NEED FOR MANAGING DEMARCATION READ VOLTAGES [patent_app_type] => utility [patent_app_number] => 18/182305 [patent_app_country] => US [patent_app_date] => 2023-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7494 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18182305 [rel_patent_id] =>[rel_patent_doc_number] =>)