Search

Mushfique Siddique

Examiner (ID: 16359, Phone: (571)270-0424 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
838
Issued Applications
687
Pending Applications
93
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18488140 [patent_doc_number] => 20230215488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => VARYING A TIME AVERAGE FOR FEEDBACK OF A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/120136 [patent_app_country] => US [patent_app_date] => 2023-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12152 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18120136 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/120136
Varying a time average for feedback of a memory system Mar 9, 2023 Issued
Array ( [id] => 19070827 [patent_doc_number] => 20240105253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/119690 [patent_app_country] => US [patent_app_date] => 2023-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3853 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18119690 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/119690
SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE Mar 8, 2023 Pending
Array ( [id] => 18631502 [patent_doc_number] => 20230290404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/180117 [patent_app_country] => US [patent_app_date] => 2023-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7373 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 485 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18180117 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/180117
Memory device with single-transistor DRAM cells with no capacitors, and memory cells stacked in the vertical direction using gate-all-around (GAA) technology Mar 6, 2023 Issued
Array ( [id] => 18631502 [patent_doc_number] => 20230290404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/180117 [patent_app_country] => US [patent_app_date] => 2023-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7373 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 485 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18180117 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/180117
Memory device with single-transistor DRAM cells with no capacitors, and memory cells stacked in the vertical direction using gate-all-around (GAA) technology Mar 6, 2023 Issued
Array ( [id] => 19900032 [patent_doc_number] => 12277964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-15 [patent_title] => Memory device and sense amplifier capable of performing in-memory logical not operation and computing [patent_app_type] => utility [patent_app_number] => 18/178915 [patent_app_country] => US [patent_app_date] => 2023-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18178915 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/178915
Memory device and sense amplifier capable of performing in-memory logical not operation and computing Mar 5, 2023 Issued
Array ( [id] => 20161178 [patent_doc_number] => 12387811 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Semiconductor memory device including an on-die ECC engine [patent_app_type] => utility [patent_app_number] => 18/174186 [patent_app_country] => US [patent_app_date] => 2023-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 5636 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18174186 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/174186
Semiconductor memory device including an on-die ECC engine Feb 23, 2023 Issued
Array ( [id] => 18587659 [patent_doc_number] => 20230269924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/172136 [patent_app_country] => US [patent_app_date] => 2023-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7464 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 392 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18172136 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/172136
SEMICONDUCTOR MEMORY DEVICE Feb 20, 2023 Abandoned
Array ( [id] => 18439687 [patent_doc_number] => 20230186982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => SEMICONDUCTOR DEVICE FOR SELECTIVELY PERFORMING ISOLATION FUNCTION AND LAYOUT DISPLACEMENT METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/164199 [patent_app_country] => US [patent_app_date] => 2023-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18164199 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/164199
Semiconductor device for selectively performing isolation function and layout displacement method thereof Feb 2, 2023 Issued
Array ( [id] => 18439680 [patent_doc_number] => 20230186975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => APPARATUSES AND METHODS FOR LOGIC/MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/105442 [patent_app_country] => US [patent_app_date] => 2023-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13844 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18105442 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/105442
Apparatuses and methods for logic/memory devices Feb 2, 2023 Issued
Array ( [id] => 18967206 [patent_doc_number] => 11900984 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-13 [patent_title] => Data destruction [patent_app_type] => utility [patent_app_number] => 18/104069 [patent_app_country] => US [patent_app_date] => 2023-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 14590 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18104069 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/104069
Data destruction Jan 30, 2023 Issued
Array ( [id] => 18439704 [patent_doc_number] => 20230186999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => METHOD FOR CHECKING THE ERASING PHASE OF A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/103226 [patent_app_country] => US [patent_app_date] => 2023-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18103226 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/103226
Method for checking the erasing phase of a memory device Jan 29, 2023 Issued
Array ( [id] => 19100786 [patent_doc_number] => 20240120014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => TEST CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/100969 [patent_app_country] => US [patent_app_date] => 2023-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7785 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18100969 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/100969
Test circuit for detecting word line defect and semiconductor apparatus including the same Jan 23, 2023 Issued
Array ( [id] => 20214962 [patent_doc_number] => 12411614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Memory device for suppressing hot carrier injection and method of operating the same [patent_app_type] => utility [patent_app_number] => 18/099386 [patent_app_country] => US [patent_app_date] => 2023-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 12451 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18099386 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/099386
Memory device for suppressing hot carrier injection and method of operating the same Jan 19, 2023 Issued
Array ( [id] => 19321202 [patent_doc_number] => 20240242748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => FLEXIBLE SRAM PRE-CHARGE SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 18/154436 [patent_app_country] => US [patent_app_date] => 2023-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3493 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18154436 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/154436
FLEXIBLE SRAM PRE-CHARGE SYSTEMS AND METHODS Jan 12, 2023 Pending
Array ( [id] => 18379418 [patent_doc_number] => 20230154507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => BIT LINE LOGIC CIRCUITS AND METHODS [patent_app_type] => utility [patent_app_number] => 18/153464 [patent_app_country] => US [patent_app_date] => 2023-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18153464 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/153464
Bit line logic circuits and methods Jan 11, 2023 Issued
Array ( [id] => 18366427 [patent_doc_number] => 20230148018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => READ-TIME OVERHEAD AND POWER OPTIMIZATIONS WITH COMMAND QUEUES IN MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/095646 [patent_app_country] => US [patent_app_date] => 2023-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12922 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18095646 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/095646
Read-time overhead and power optimizations with command queues in memory device Jan 10, 2023 Issued
Array ( [id] => 19906290 [patent_doc_number] => 12283302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Memory circuit, signal transmission system and signal transmission method [patent_app_type] => utility [patent_app_number] => 18/151459 [patent_app_country] => US [patent_app_date] => 2023-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 0 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18151459 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/151459
Memory circuit, signal transmission system and signal transmission method Jan 7, 2023 Issued
Array ( [id] => 18454802 [patent_doc_number] => 20230196082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => BAYESIAN NEURAL NETWORK WITH RESISTIVE MEMORY HARDWARE ACCELERATOR AND METHOD FOR PROGRAMMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/067088 [patent_app_country] => US [patent_app_date] => 2022-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6522 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18067088 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/067088
BAYESIAN NEURAL NETWORK WITH RESISTIVE MEMORY HARDWARE ACCELERATOR AND METHOD FOR PROGRAMMING THE SAME Dec 15, 2022 Pending
Array ( [id] => 19330435 [patent_doc_number] => 12048135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Four-poly-pitch SRAM cell with backside metal tracks [patent_app_type] => utility [patent_app_number] => 18/064859 [patent_app_country] => US [patent_app_date] => 2022-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8349 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18064859 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/064859
Four-poly-pitch SRAM cell with backside metal tracks Dec 11, 2022 Issued
Array ( [id] => 19062894 [patent_doc_number] => 11942139 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Performing refresh operations on memory cells [patent_app_type] => utility [patent_app_number] => 18/075570 [patent_app_country] => US [patent_app_date] => 2022-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6760 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18075570 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/075570
Performing refresh operations on memory cells Dec 5, 2022 Issued
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