
Mushfique Siddique
Examiner (ID: 1672, Phone: (571)270-0424 , Office: P/2825 )
| Most Active Art Unit | 2825 |
| Art Unit(s) | 2825 |
| Total Applications | 886 |
| Issued Applications | 722 |
| Pending Applications | 91 |
| Abandoned Applications | 88 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
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