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Mushfique Siddique

Examiner (ID: 16359, Phone: (571)270-0424 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825
Total Applications
838
Issued Applications
687
Pending Applications
93
Abandoned Applications
85

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19062897 [patent_doc_number] => 11942142 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Memory subword driver circuits with common transistors at word lines [patent_app_type] => utility [patent_app_number] => 17/931457 [patent_app_country] => US [patent_app_date] => 2022-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12172 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17931457 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/931457
Memory subword driver circuits with common transistors at word lines Sep 11, 2022 Issued
Array ( [id] => 18623583 [patent_doc_number] => 11756636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Determining threshold values for voltage distribution metrics [patent_app_type] => utility [patent_app_number] => 17/939594 [patent_app_country] => US [patent_app_date] => 2022-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11624 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17939594 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/939594
Determining threshold values for voltage distribution metrics Sep 6, 2022 Issued
Array ( [id] => 19494101 [patent_doc_number] => 12112822 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Multi-channel memory device capable of switching redundancy memory blocks to replace failed memory block [patent_app_type] => utility [patent_app_number] => 17/903052 [patent_app_country] => US [patent_app_date] => 2022-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3429 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17903052 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/903052
Multi-channel memory device capable of switching redundancy memory blocks to replace failed memory block Sep 5, 2022 Issued
Array ( [id] => 18112674 [patent_doc_number] => 20230005554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => ROBUSTNESS-AWARE NAND FLASH MANAGEMENT [patent_app_type] => utility [patent_app_number] => 17/903390 [patent_app_country] => US [patent_app_date] => 2022-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5018 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17903390 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/903390
Robustness-aware NAND flash management Sep 5, 2022 Issued
Array ( [id] => 18990854 [patent_doc_number] => 20240062823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => MIXED WRITE CURSOR FOR BLOCK STRIPE WRITING [patent_app_type] => utility [patent_app_number] => 17/823674 [patent_app_country] => US [patent_app_date] => 2022-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14312 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17823674 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/823674
Mixed write cursor for block stripe writing Aug 30, 2022 Issued
Array ( [id] => 19007394 [patent_doc_number] => 20240071465 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => STRUCTURES FOR WORD LINE MULTIPLEXING IN THREE-DIMENSIONAL MEMORY ARRAYS [patent_app_type] => utility [patent_app_number] => 17/821645 [patent_app_country] => US [patent_app_date] => 2022-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17821645 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/821645
Structures for word line multiplexing in three-dimensional memory arrays Aug 22, 2022 Issued
Array ( [id] => 19812201 [patent_doc_number] => 12243610 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Memory with parallel main and test interfaces [patent_app_type] => utility [patent_app_number] => 17/821676 [patent_app_country] => US [patent_app_date] => 2022-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 14673 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17821676 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/821676
Memory with parallel main and test interfaces Aug 22, 2022 Issued
Array ( [id] => 18192904 [patent_doc_number] => 20230046423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => MAGNETORESISTIVE MEMORY CELL, WRITE CONTROL METHOD AND MEMORY COMPUTING MODULE [patent_app_type] => utility [patent_app_number] => 17/821783 [patent_app_country] => US [patent_app_date] => 2022-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17821783 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/821783
In-memory computing using SOT-MRAM Aug 22, 2022 Issued
Array ( [id] => 19007398 [patent_doc_number] => 20240071469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => MEMORY WITH SINGLE TRANSISTOR SUB-WORD LINE DRIVERS, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS [patent_app_type] => utility [patent_app_number] => 17/894089 [patent_app_country] => US [patent_app_date] => 2022-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17894089 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/894089
MEMORY WITH SINGLE TRANSISTOR SUB-WORD LINE DRIVERS, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS Aug 22, 2022 Pending
Array ( [id] => 19328604 [patent_doc_number] => 12046293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Memory device and method for operating selective erase scheme [patent_app_type] => utility [patent_app_number] => 17/820906 [patent_app_country] => US [patent_app_date] => 2022-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4905 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17820906 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/820906
Memory device and method for operating selective erase scheme Aug 18, 2022 Issued
Array ( [id] => 18061424 [patent_doc_number] => 20220392510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => APPARATUSES AND METHODS FOR REDUNDANCE MATCH CONTROL AT REFRESH TO DISABLE WORDLINE ACTIVATION [patent_app_type] => utility [patent_app_number] => 17/889183 [patent_app_country] => US [patent_app_date] => 2022-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6144 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17889183 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/889183
Apparatuses and methods for skipping wordline activation of defective memory during refresh operations Aug 15, 2022 Issued
Array ( [id] => 19828597 [patent_doc_number] => 12249388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => Memory system and nonvolatile memory for improving reliability of stored data and shortening operation time [patent_app_type] => utility [patent_app_number] => 17/887985 [patent_app_country] => US [patent_app_date] => 2022-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 6847 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17887985 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/887985
Memory system and nonvolatile memory for improving reliability of stored data and shortening operation time Aug 14, 2022 Issued
Array ( [id] => 19046464 [patent_doc_number] => 11935583 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Integrated assemblies [patent_app_type] => utility [patent_app_number] => 17/887226 [patent_app_country] => US [patent_app_date] => 2022-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5806 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17887226 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/887226
Integrated assemblies Aug 11, 2022 Issued
Array ( [id] => 18974952 [patent_doc_number] => 20240055044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => SYSTEMS AND METHODS FOR CONTROLLING COMMON MODE LEVEL FOR SENSE AMPLIFIER CIRCUITRY [patent_app_type] => utility [patent_app_number] => 17/884261 [patent_app_country] => US [patent_app_date] => 2022-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7259 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884261 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/884261
Systems and methods for controlling common mode level for sense amplifier circuitry Aug 8, 2022 Issued
Array ( [id] => 18488138 [patent_doc_number] => 20230215486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => MEMORY DEVICE AND OPERATING SYSTEM [patent_app_type] => utility [patent_app_number] => 17/884053 [patent_app_country] => US [patent_app_date] => 2022-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5956 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884053 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/884053
Memory device and memory system with a self-refresh function Aug 8, 2022 Issued
Array ( [id] => 18585722 [patent_doc_number] => 20230267986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => TWO-STAGE VOLTAGE CALIBRATION UPON POWER-UP OF MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/883392 [patent_app_country] => US [patent_app_date] => 2022-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8040 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17883392 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/883392
Two-stage voltage calibration upon power-up of memory device Aug 7, 2022 Issued
Array ( [id] => 18008196 [patent_doc_number] => 20220366963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => FLASH MEMORY STORAGE APPARATUS AND A BIASING METHOD THEREOF, WHICH CAN REDUCE A GATE INDUCED DRAIN LEAKAGE (GIDL) AND IMPROVE RELIABILITY OF MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/874296 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2836 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17874296 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/874296
FLASH MEMORY STORAGE APPARATUS AND A BIASING METHOD THEREOF, WHICH CAN REDUCE A GATE INDUCED DRAIN LEAKAGE (GIDL) AND IMPROVE RELIABILITY OF MEMORY CELLS Jul 26, 2022 Abandoned
Array ( [id] => 18630682 [patent_doc_number] => 20230289577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => NEURAL NETWORK SYSTEM, HIGH DENSITY EMBEDDED-ARTIFICIAL SYNAPTIC ELEMENT AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/813598 [patent_app_country] => US [patent_app_date] => 2022-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6233 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17813598 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/813598
NEURAL NETWORK SYSTEM, HIGH DENSITY EMBEDDED-ARTIFICIAL SYNAPTIC ELEMENT AND OPERATING METHOD THEREOF Jul 18, 2022 Pending
Array ( [id] => 20243930 [patent_doc_number] => 12424260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Triggering a refresh for non-volatile memory [patent_app_type] => utility [patent_app_number] => 17/868074 [patent_app_country] => US [patent_app_date] => 2022-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 14822 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17868074 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/868074
Triggering a refresh for non-volatile memory Jul 18, 2022 Issued
Array ( [id] => 19679110 [patent_doc_number] => 12190981 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Memory array having error checking and correction circuit [patent_app_type] => utility [patent_app_number] => 17/866558 [patent_app_country] => US [patent_app_date] => 2022-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5621 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17866558 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/866558
Memory array having error checking and correction circuit Jul 17, 2022 Issued
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