
My Trang Ton
Examiner (ID: 3916, Phone: (571)272-1754 , Office: P/3992 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 3992, 2816, 2504 |
| Total Applications | 1512 |
| Issued Applications | 1345 |
| Pending Applications | 95 |
| Abandoned Applications | 73 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 470123
[patent_doc_number] => 07233197
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-06-19
[patent_title] => 'Methods and systems for reducing leakage current in semiconductor circuits'
[patent_app_type] => utility
[patent_app_number] => 11/006974
[patent_app_country] => US
[patent_app_date] => 2004-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 21
[patent_no_of_words] => 9389
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/233/07233197.pdf
[firstpage_image] =>[orig_patent_app_number] => 11006974
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/006974 | Methods and systems for reducing leakage current in semiconductor circuits | Dec 6, 2004 | Issued |
Array
(
[id] => 5838931
[patent_doc_number] => 20060119411
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-08
[patent_title] => 'Switched capacitor sampler circuit and method therefor'
[patent_app_type] => utility
[patent_app_number] => 11/003288
[patent_app_country] => US
[patent_app_date] => 2004-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7608
[patent_no_of_claims] => 41
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0119/20060119411.pdf
[firstpage_image] =>[orig_patent_app_number] => 11003288
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/003288 | Switched capacitor sampler circuit and method therefor | Dec 2, 2004 | Issued |
Array
(
[id] => 566375
[patent_doc_number] => 07157956
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-01-02
[patent_title] => 'Switched capacitor input circuit and method therefor'
[patent_app_type] => utility
[patent_app_number] => 11/004387
[patent_app_country] => US
[patent_app_date] => 2004-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 7485
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/157/07157956.pdf
[firstpage_image] =>[orig_patent_app_number] => 11004387
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/004387 | Switched capacitor input circuit and method therefor | Dec 2, 2004 | Issued |
Array
(
[id] => 5612123
[patent_doc_number] => 20060114049
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-01
[patent_title] => 'Switched capacitor mutual charging system and method'
[patent_app_type] => utility
[patent_app_number] => 11/001401
[patent_app_country] => US
[patent_app_date] => 2004-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4396
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0114/20060114049.pdf
[firstpage_image] =>[orig_patent_app_number] => 11001401
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/001401 | Switched capacitor mutual charging system and method | Nov 30, 2004 | Issued |
Array
(
[id] => 7095512
[patent_doc_number] => 20050127970
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-16
[patent_title] => 'Input/output block with programmable hysteresis'
[patent_app_type] => utility
[patent_app_number] => 10/993132
[patent_app_country] => US
[patent_app_date] => 2004-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 2814
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0127/20050127970.pdf
[firstpage_image] =>[orig_patent_app_number] => 10993132
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/993132 | Input/output block with programmable hysteresis | Nov 17, 2004 | Issued |
Array
(
[id] => 6937011
[patent_doc_number] => 20050110572
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-26
[patent_title] => 'Amplifier; and transmitter and communication device incorporating the same'
[patent_app_type] => utility
[patent_app_number] => 10/988499
[patent_app_country] => US
[patent_app_date] => 2004-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 8246
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0110/20050110572.pdf
[firstpage_image] =>[orig_patent_app_number] => 10988499
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/988499 | Amplifier; and transmitter and communication device incorporating the same | Nov 15, 2004 | Issued |
Array
(
[id] => 7188399
[patent_doc_number] => 20050162803
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-28
[patent_title] => 'Control circuit for an inductive load driver'
[patent_app_type] => utility
[patent_app_number] => 10/989102
[patent_app_country] => US
[patent_app_date] => 2004-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3196
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0162/20050162803.pdf
[firstpage_image] =>[orig_patent_app_number] => 10989102
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/989102 | Control circuit for an inductive load driver | Nov 14, 2004 | Issued |
Array
(
[id] => 5774807
[patent_doc_number] => 20060103447
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-18
[patent_title] => 'Method and apparatus for summing DC voltages'
[patent_app_type] => utility
[patent_app_number] => 10/988156
[patent_app_country] => US
[patent_app_date] => 2004-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4744
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0103/20060103447.pdf
[firstpage_image] =>[orig_patent_app_number] => 10988156
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/988156 | Method and apparatus for summing DC voltages | Nov 11, 2004 | Issued |
Array
(
[id] => 660113
[patent_doc_number] => 07106111
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-12
[patent_title] => 'Clock adjustment'
[patent_app_type] => utility
[patent_app_number] => 10/987016
[patent_app_country] => US
[patent_app_date] => 2004-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 6982
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/106/07106111.pdf
[firstpage_image] =>[orig_patent_app_number] => 10987016
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/987016 | Clock adjustment | Nov 11, 2004 | Issued |
Array
(
[id] => 532114
[patent_doc_number] => 07183813
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-27
[patent_title] => 'Differential signaling driver'
[patent_app_type] => utility
[patent_app_number] => 10/985661
[patent_app_country] => US
[patent_app_date] => 2004-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 4094
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/183/07183813.pdf
[firstpage_image] =>[orig_patent_app_number] => 10985661
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/985661 | Differential signaling driver | Nov 9, 2004 | Issued |
Array
(
[id] => 7140992
[patent_doc_number] => 20050116771
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-02
[patent_title] => 'Power amplification circuits'
[patent_app_type] => utility
[patent_app_number] => 10/985120
[patent_app_country] => US
[patent_app_date] => 2004-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7900
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0116/20050116771.pdf
[firstpage_image] =>[orig_patent_app_number] => 10985120
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/985120 | Power amplification circuits | Nov 9, 2004 | Issued |
Array
(
[id] => 540699
[patent_doc_number] => 07173477
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-02-06
[patent_title] => 'Variable capacitance charge pump system and method'
[patent_app_type] => utility
[patent_app_number] => 10/978045
[patent_app_country] => US
[patent_app_date] => 2004-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2862
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/173/07173477.pdf
[firstpage_image] =>[orig_patent_app_number] => 10978045
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/978045 | Variable capacitance charge pump system and method | Oct 28, 2004 | Issued |
Array
(
[id] => 7621970
[patent_doc_number] => 06977531
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-12-20
[patent_title] => 'RF signal peak detector'
[patent_app_type] => utility
[patent_app_number] => 10/973722
[patent_app_country] => US
[patent_app_date] => 2004-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 5192
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/977/06977531.pdf
[firstpage_image] =>[orig_patent_app_number] => 10973722
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/973722 | RF signal peak detector | Oct 25, 2004 | Issued |
Array
(
[id] => 5713623
[patent_doc_number] => 20060076986
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-04-13
[patent_title] => 'Half-bridge inverter of dual N-MOS with a push/pull control chip'
[patent_app_type] => utility
[patent_app_number] => 10/959148
[patent_app_country] => US
[patent_app_date] => 2004-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3211
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0076/20060076986.pdf
[firstpage_image] =>[orig_patent_app_number] => 10959148
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/959148 | Half-bridge inverter of dual N-MOS with a push/pull control chip | Oct 6, 2004 | Issued |
Array
(
[id] => 509260
[patent_doc_number] => 07202723
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-10
[patent_title] => 'Adjustable switchpoint receiver'
[patent_app_type] => utility
[patent_app_number] => 10/960568
[patent_app_country] => US
[patent_app_date] => 2004-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 4827
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/202/07202723.pdf
[firstpage_image] =>[orig_patent_app_number] => 10960568
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/960568 | Adjustable switchpoint receiver | Oct 6, 2004 | Issued |
Array
(
[id] => 7609304
[patent_doc_number] => 06998885
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-02-14
[patent_title] => 'Apparatus and method for delay matching of full and divided clock signals'
[patent_app_type] => utility
[patent_app_number] => 10/959512
[patent_app_country] => US
[patent_app_date] => 2004-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4503
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/998/06998885.pdf
[firstpage_image] =>[orig_patent_app_number] => 10959512
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/959512 | Apparatus and method for delay matching of full and divided clock signals | Oct 6, 2004 | Issued |
Array
(
[id] => 7101924
[patent_doc_number] => 20050104650
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-19
[patent_title] => 'Method for switching driving of a semiconductor switching element'
[patent_app_type] => utility
[patent_app_number] => 10/959901
[patent_app_country] => US
[patent_app_date] => 2004-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7341
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0104/20050104650.pdf
[firstpage_image] =>[orig_patent_app_number] => 10959901
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/959901 | Method for switching driving of a semiconductor switching element | Oct 5, 2004 | Issued |
Array
(
[id] => 739740
[patent_doc_number] => 07034583
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-04-25
[patent_title] => 'Versatile system for output energy limiting circuitry'
[patent_app_type] => utility
[patent_app_number] => 10/959262
[patent_app_country] => US
[patent_app_date] => 2004-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 5351
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/034/07034583.pdf
[firstpage_image] =>[orig_patent_app_number] => 10959262
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/959262 | Versatile system for output energy limiting circuitry | Oct 5, 2004 | Issued |
Array
(
[id] => 634987
[patent_doc_number] => 07129758
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-10-31
[patent_title] => 'Load driving circuit with current detection capability'
[patent_app_type] => utility
[patent_app_number] => 10/957048
[patent_app_country] => US
[patent_app_date] => 2004-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 6956
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/129/07129758.pdf
[firstpage_image] =>[orig_patent_app_number] => 10957048
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/957048 | Load driving circuit with current detection capability | Sep 30, 2004 | Issued |
Array
(
[id] => 606939
[patent_doc_number] => 07154308
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-12-26
[patent_title] => 'Driver circuit with gradual voltage ramp up and ramp down'
[patent_app_type] => utility
[patent_app_number] => 10/956290
[patent_app_country] => US
[patent_app_date] => 2004-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 4333
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/154/07154308.pdf
[firstpage_image] =>[orig_patent_app_number] => 10956290
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/956290 | Driver circuit with gradual voltage ramp up and ramp down | Sep 29, 2004 | Issued |