My Trang Ton

Array ( [id] => 1182871 [patent_doc_number] => 06741105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-25 [patent_title] => 'Differential circuit and peak hold circuit including differential circuit' [patent_app_type] => B2 [patent_app_number] => 10/418197 [patent_app_country] => US [patent_app_date] => 2003-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4771 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/741/06741105.pdf [firstpage_image] =>[orig_patent_app_number] => 10418197 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 677466 [patent_doc_number] => 07088147 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'Sample and hold circuits and methods with offset error correction and systems using the same' [patent_app_type] => utility [patent_app_number] => 10/417443 [patent_app_country] => US [patent_app_date] => 2003-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3270 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/088/07088147.pdf [firstpage_image] =>[orig_patent_app_number] => 10417443 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6807593 [patent_doc_number] => 20030197532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Overcurrent protection structure of load driving circuit' [patent_app_type] => new [patent_app_number] => 10/413090 [patent_app_country] => US [patent_app_date] => 2003-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4924 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20030197532.pdf [firstpage_image] =>[orig_patent_app_number] => 10413090 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7445582 [patent_doc_number] => 20040196072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-07 [patent_title] => 'CIRCUIT AND METHOD FOR OVER-CURRENT SENSING AND CONTROL' [patent_app_type] => new [patent_app_number] => 10/408531 [patent_app_country] => US [patent_app_date] => 2003-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4682 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20040196072.pdf [firstpage_image] =>[orig_patent_app_number] => 10408531 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1177123 [patent_doc_number] => 06750693 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-15 [patent_title] => 'Clock generation circuits and methods with minimal glitch generation and systems using the same' [patent_app_type] => B1 [patent_app_number] => 10/407672 [patent_app_country] => US [patent_app_date] => 2003-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3330 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/750/06750693.pdf [firstpage_image] =>[orig_patent_app_number] => 10407672 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7335232 [patent_doc_number] => 20040189368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-30 [patent_title] => 'Adaptive delay of timing control signals' [patent_app_type] => new [patent_app_number] => 10/402137 [patent_app_country] => US [patent_app_date] => 2003-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4641 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20040189368.pdf [firstpage_image] =>[orig_patent_app_number] => 10402137 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 951745 [patent_doc_number] => 06960950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-01 [patent_title] => 'Circuit and method for generating a clock signal' [patent_app_type] => utility [patent_app_number] => 10/400147 [patent_app_country] => US [patent_app_date] => 2003-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 5911 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/960/06960950.pdf [firstpage_image] =>[orig_patent_app_number] => 10400147 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1086822 [patent_doc_number] => 06831487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-14 [patent_title] => 'Pattern based dynamic drive current balancing for data transmission' [patent_app_type] => B2 [patent_app_number] => 10/393303 [patent_app_country] => US [patent_app_date] => 2003-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3189 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/831/06831487.pdf [firstpage_image] =>[orig_patent_app_number] => 10393303 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7619575 [patent_doc_number] => 06943611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-13 [patent_title] => 'Drive control circuit for a junction field-effect transistor' [patent_app_type] => utility [patent_app_number] => 10/392704 [patent_app_country] => US [patent_app_date] => 2003-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2443 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/943/06943611.pdf [firstpage_image] =>[orig_patent_app_number] => 10392704 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6768396 [patent_doc_number] => 20030214336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-20 [patent_title] => 'Temperature sensing circuit' [patent_app_type] => new [patent_app_number] => 10/390699 [patent_app_country] => US [patent_app_date] => 2003-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4949 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20030214336.pdf [firstpage_image] =>[orig_patent_app_number] => 10390699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 747460 [patent_doc_number] => 07026858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-11 [patent_title] => 'Switch semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/390777 [patent_app_country] => US [patent_app_date] => 2003-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5683 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/026/07026858.pdf [firstpage_image] =>[orig_patent_app_number] => 10390777 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1064093 [patent_doc_number] => 06850104 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-01 [patent_title] => 'Master-slave latch with transparent mode' [patent_app_type] => utility [patent_app_number] => 10/385114 [patent_app_country] => US [patent_app_date] => 2003-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5398 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/850/06850104.pdf [firstpage_image] =>[orig_patent_app_number] => 10385114 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7395388 [patent_doc_number] => 20040174196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Circuit for modifying a clock signal to achieve a predetermined duty cycle' [patent_app_type] => new [patent_app_number] => 10/384262 [patent_app_country] => US [patent_app_date] => 2003-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4803 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20040174196.pdf [firstpage_image] =>[orig_patent_app_number] => 10384262 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1019070 [patent_doc_number] => 06891423 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-10 [patent_title] => 'Quadrature switching mixer with reduced leakage' [patent_app_type] => utility [patent_app_number] => 10/383370 [patent_app_country] => US [patent_app_date] => 2003-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3395 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/891/06891423.pdf [firstpage_image] =>[orig_patent_app_number] => 10383370 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7395369 [patent_doc_number] => 20040174192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Method and apparatus for reconfigurable frequency generation' [patent_app_type] => new [patent_app_number] => 10/382696 [patent_app_country] => US [patent_app_date] => 2003-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3101 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20040174192.pdf [firstpage_image] =>[orig_patent_app_number] => 10382696 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1214795 [patent_doc_number] => 06710639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-23 [patent_title] => 'Emitter turn-off thyristors and their drive circuits' [patent_app_type] => B2 [patent_app_number] => 10/378606 [patent_app_country] => US [patent_app_date] => 2003-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8539 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/710/06710639.pdf [firstpage_image] =>[orig_patent_app_number] => 10378606 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1203839 [patent_doc_number] => 06720807 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-13 [patent_title] => 'Semiconductor device with clock generation circuit' [patent_app_type] => B1 [patent_app_number] => 10/377738 [patent_app_country] => US [patent_app_date] => 2003-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 11185 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/720/06720807.pdf [firstpage_image] =>[orig_patent_app_number] => 10377738 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1015353 [patent_doc_number] => 06894552 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-17 [patent_title] => 'Low-jitter delay cell' [patent_app_type] => utility [patent_app_number] => 10/376664 [patent_app_country] => US [patent_app_date] => 2003-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2436 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/894/06894552.pdf [firstpage_image] =>[orig_patent_app_number] => 10376664 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1218636 [patent_doc_number] => 06707332 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-16 [patent_title] => 'Clock generating circuit and method thereof' [patent_app_type] => B1 [patent_app_number] => 10/248870 [patent_app_country] => US [patent_app_date] => 2003-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4855 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/707/06707332.pdf [firstpage_image] =>[orig_patent_app_number] => 10248870 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7130575 [patent_doc_number] => 20040041604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Phase jumping locked loop circuit' [patent_app_type] => new [patent_app_number] => 10/374251 [patent_app_country] => US [patent_app_date] => 2003-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 26931 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20040041604.pdf [firstpage_image] =>[orig_patent_app_number] => 10374251 [rel_patent_id] =>[rel_patent_doc_number] =>)