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Examiner (ID: 3916, Phone: (571)272-1754 , Office: P/3992 )

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2504
Total Applications
1512
Issued Applications
1345
Pending Applications
95
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7329773 [patent_doc_number] => 20040130365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-08 [patent_title] => 'HIGH RESOLUTION INTERLEAVED DELAY CHAIN' [patent_app_type] => new [patent_app_number] => 10/337606 [patent_app_country] => US [patent_app_date] => 2003-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3869 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20040130365.pdf [firstpage_image] =>[orig_patent_app_number] => 10337606 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/337606
High resolution interleaved delay chain Jan 6, 2003 Issued
Array ( [id] => 1066700 [patent_doc_number] => 06847251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-25 [patent_title] => 'Differential charge pump circuit' [patent_app_type] => utility [patent_app_number] => 10/336748 [patent_app_country] => US [patent_app_date] => 2003-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3102 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/847/06847251.pdf [firstpage_image] =>[orig_patent_app_number] => 10336748 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/336748
Differential charge pump circuit Jan 5, 2003 Issued
Array ( [id] => 7349869 [patent_doc_number] => 20040012427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'DELAY LOCKED LOOP DLL IN SEMICONDUCTOR DEVICE' [patent_app_type] => new [patent_app_number] => 10/331338 [patent_app_country] => US [patent_app_date] => 2002-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2181 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20040012427.pdf [firstpage_image] =>[orig_patent_app_number] => 10331338 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/331338
Delay locked loop DLL in semiconductor device Dec 30, 2002 Issued
Array ( [id] => 1057243 [patent_doc_number] => 06856181 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-02-15 [patent_title] => 'Stability robustness using a non-integer order filter in a circuit' [patent_app_type] => utility [patent_app_number] => 10/335457 [patent_app_country] => US [patent_app_date] => 2002-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3049 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/856/06856181.pdf [firstpage_image] =>[orig_patent_app_number] => 10335457 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/335457
Stability robustness using a non-integer order filter in a circuit Dec 29, 2002 Issued
Array ( [id] => 6820325 [patent_doc_number] => 20030218486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-27 [patent_title] => 'Digital DLL apparatus for correcting duty cycle and method thereof' [patent_app_type] => new [patent_app_number] => 10/335655 [patent_app_country] => US [patent_app_date] => 2002-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6559 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20030218486.pdf [firstpage_image] =>[orig_patent_app_number] => 10335655 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/335655
Digital DLL apparatus for correcting duty cycle and method thereof Dec 29, 2002 Issued
Array ( [id] => 688122 [patent_doc_number] => 07078946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'Analog PLL with switched capacitor resampling filter' [patent_app_type] => utility [patent_app_number] => 10/330836 [patent_app_country] => US [patent_app_date] => 2002-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 27 [patent_no_of_words] => 6960 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/078/07078946.pdf [firstpage_image] =>[orig_patent_app_number] => 10330836 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/330836
Analog PLL with switched capacitor resampling filter Dec 26, 2002 Issued
Array ( [id] => 1246946 [patent_doc_number] => 06677794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-13 [patent_title] => 'Clock synchronization device' [patent_app_type] => B2 [patent_app_number] => 10/330863 [patent_app_country] => US [patent_app_date] => 2002-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4607 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/677/06677794.pdf [firstpage_image] =>[orig_patent_app_number] => 10330863 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/330863
Clock synchronization device Dec 26, 2002 Issued
Array ( [id] => 6827956 [patent_doc_number] => 20030179014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'Frequency comparator with malfunction reduced and phase-locked state detecting circuit using the same' [patent_app_type] => new [patent_app_number] => 10/327864 [patent_app_country] => US [patent_app_date] => 2002-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8617 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20030179014.pdf [firstpage_image] =>[orig_patent_app_number] => 10327864 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/327864
Frequency comparator with malfunction reduced and phase-locked state detecting circuit using the same Dec 25, 2002 Issued
Array ( [id] => 7459600 [patent_doc_number] => 20040119509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Single ended clock signal generator having a differential output' [patent_app_type] => new [patent_app_number] => 10/327217 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3564 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20040119509.pdf [firstpage_image] =>[orig_patent_app_number] => 10327217 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/327217
Single ended clock signal generator having a differential output Dec 19, 2002 Issued
Array ( [id] => 7616560 [patent_doc_number] => 06946882 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-20 [patent_title] => 'Current sense amplifier' [patent_app_type] => utility [patent_app_number] => 10/326367 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 13181 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/946/06946882.pdf [firstpage_image] =>[orig_patent_app_number] => 10326367 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/326367
Current sense amplifier Dec 19, 2002 Issued
Array ( [id] => 6863923 [patent_doc_number] => 20030189449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-09 [patent_title] => 'Designs of integrated circuits for high-speed signals and methods therefor' [patent_app_type] => new [patent_app_number] => 10/325038 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5958 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20030189449.pdf [firstpage_image] =>[orig_patent_app_number] => 10325038 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/325038
Designs of integrated circuits for high-speed signals and methods therefor Dec 19, 2002 Issued
Array ( [id] => 747404 [patent_doc_number] => 07026845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-11 [patent_title] => 'Electronic circuit for converting a current signal to a voltage signal' [patent_app_type] => utility [patent_app_number] => 10/502154 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2815 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/026/07026845.pdf [firstpage_image] =>[orig_patent_app_number] => 10502154 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/502154
Electronic circuit for converting a current signal to a voltage signal Dec 19, 2002 Issued
Array ( [id] => 1222480 [patent_doc_number] => 06703888 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Method of operating circuit with FET transistor pair' [patent_app_type] => B1 [patent_app_number] => 10/327586 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3990 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/703/06703888.pdf [firstpage_image] =>[orig_patent_app_number] => 10327586 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/327586
Method of operating circuit with FET transistor pair Dec 19, 2002 Issued
Array ( [id] => 944452 [patent_doc_number] => 06967506 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Circuit arrangement for the discrete-time comparison of signals' [patent_app_type] => utility [patent_app_number] => 10/321154 [patent_app_country] => US [patent_app_date] => 2002-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4216 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967506.pdf [firstpage_image] =>[orig_patent_app_number] => 10321154 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/321154
Circuit arrangement for the discrete-time comparison of signals Dec 16, 2002 Issued
Array ( [id] => 7301700 [patent_doc_number] => 20040113677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => 'LEVEL SHIFTER AND VOLTAGE TRANSLATOR' [patent_app_type] => new [patent_app_number] => 10/318689 [patent_app_country] => US [patent_app_date] => 2002-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2934 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20040113677.pdf [firstpage_image] =>[orig_patent_app_number] => 10318689 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/318689
Level shifter and voltage translator Dec 11, 2002 Issued
Array ( [id] => 6916028 [patent_doc_number] => 20050093589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Circuit arrangement for the provision of an output signal with adjustable flank pitch' [patent_app_type] => utility [patent_app_number] => 10/499927 [patent_app_country] => US [patent_app_date] => 2002-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4978 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20050093589.pdf [firstpage_image] =>[orig_patent_app_number] => 10499927 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/499927
Circuit arrangement for the provision of an output signal with adjustable flank pitch Dec 10, 2002 Issued
Array ( [id] => 1060531 [patent_doc_number] => 06853219 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-08 [patent_title] => 'Charging circuit' [patent_app_type] => utility [patent_app_number] => 10/467453 [patent_app_country] => US [patent_app_date] => 2002-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7568 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/853/06853219.pdf [firstpage_image] =>[orig_patent_app_number] => 10467453 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/467453
Charging circuit Dec 9, 2002 Issued
Array ( [id] => 6795125 [patent_doc_number] => 20030173998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-18 [patent_title] => 'Sense amplifier with offset cancellation and charge-share limited swing drivers' [patent_app_type] => new [patent_app_number] => 10/313282 [patent_app_country] => US [patent_app_date] => 2002-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 16664 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20030173998.pdf [firstpage_image] =>[orig_patent_app_number] => 10313282 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/313282
Sense amplifier with offset cancellation and charge-share limited swing drivers Dec 4, 2002 Issued
Array ( [id] => 1172992 [patent_doc_number] => 06753704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-22 [patent_title] => 'Sampling phase detector' [patent_app_type] => B2 [patent_app_number] => 10/303745 [patent_app_country] => US [patent_app_date] => 2002-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3903 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/753/06753704.pdf [firstpage_image] =>[orig_patent_app_number] => 10303745 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/303745
Sampling phase detector Nov 25, 2002 Issued
Array ( [id] => 1169593 [patent_doc_number] => 06759897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-06 [patent_title] => 'Circuit for reducing second and third order intermodulation distortion for a broadband RF amplifier' [patent_app_type] => B2 [patent_app_number] => 10/303611 [patent_app_country] => US [patent_app_date] => 2002-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5364 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/759/06759897.pdf [firstpage_image] =>[orig_patent_app_number] => 10303611 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/303611
Circuit for reducing second and third order intermodulation distortion for a broadband RF amplifier Nov 24, 2002 Issued
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