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Examiner (ID: 9286)

Most Active Art Unit
2816
Art Unit(s)
2816, 2504, 3992
Total Applications
1495
Issued Applications
1343
Pending Applications
84
Abandoned Applications
72

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 944452 [patent_doc_number] => 06967506 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Circuit arrangement for the discrete-time comparison of signals' [patent_app_type] => utility [patent_app_number] => 10/321154 [patent_app_country] => US [patent_app_date] => 2002-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4216 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967506.pdf [firstpage_image] =>[orig_patent_app_number] => 10321154 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/321154
Circuit arrangement for the discrete-time comparison of signals Dec 16, 2002 Issued
Array ( [id] => 7301700 [patent_doc_number] => 20040113677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => 'LEVEL SHIFTER AND VOLTAGE TRANSLATOR' [patent_app_type] => new [patent_app_number] => 10/318689 [patent_app_country] => US [patent_app_date] => 2002-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2934 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20040113677.pdf [firstpage_image] =>[orig_patent_app_number] => 10318689 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/318689
Level shifter and voltage translator Dec 11, 2002 Issued
Array ( [id] => 6916028 [patent_doc_number] => 20050093589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Circuit arrangement for the provision of an output signal with adjustable flank pitch' [patent_app_type] => utility [patent_app_number] => 10/499927 [patent_app_country] => US [patent_app_date] => 2002-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4978 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20050093589.pdf [firstpage_image] =>[orig_patent_app_number] => 10499927 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/499927
Circuit arrangement for the provision of an output signal with adjustable flank pitch Dec 10, 2002 Issued
Array ( [id] => 1060531 [patent_doc_number] => 06853219 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-08 [patent_title] => 'Charging circuit' [patent_app_type] => utility [patent_app_number] => 10/467453 [patent_app_country] => US [patent_app_date] => 2002-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7568 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/853/06853219.pdf [firstpage_image] =>[orig_patent_app_number] => 10467453 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/467453
Charging circuit Dec 9, 2002 Issued
Array ( [id] => 6795125 [patent_doc_number] => 20030173998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-18 [patent_title] => 'Sense amplifier with offset cancellation and charge-share limited swing drivers' [patent_app_type] => new [patent_app_number] => 10/313282 [patent_app_country] => US [patent_app_date] => 2002-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 16664 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20030173998.pdf [firstpage_image] =>[orig_patent_app_number] => 10313282 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/313282
Sense amplifier with offset cancellation and charge-share limited swing drivers Dec 4, 2002 Issued
Array ( [id] => 1172992 [patent_doc_number] => 06753704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-22 [patent_title] => 'Sampling phase detector' [patent_app_type] => B2 [patent_app_number] => 10/303745 [patent_app_country] => US [patent_app_date] => 2002-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3903 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/753/06753704.pdf [firstpage_image] =>[orig_patent_app_number] => 10303745 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/303745
Sampling phase detector Nov 25, 2002 Issued
Array ( [id] => 1169593 [patent_doc_number] => 06759897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-06 [patent_title] => 'Circuit for reducing second and third order intermodulation distortion for a broadband RF amplifier' [patent_app_type] => B2 [patent_app_number] => 10/303611 [patent_app_country] => US [patent_app_date] => 2002-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5364 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/759/06759897.pdf [firstpage_image] =>[orig_patent_app_number] => 10303611 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/303611
Circuit for reducing second and third order intermodulation distortion for a broadband RF amplifier Nov 24, 2002 Issued
Array ( [id] => 6799810 [patent_doc_number] => 20030094974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-22 [patent_title] => 'Clock\'s out-of-synchronism state detection circuit and optical receiving device using the same' [patent_app_type] => new [patent_app_number] => 10/300526 [patent_app_country] => US [patent_app_date] => 2002-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3874 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20030094974.pdf [firstpage_image] =>[orig_patent_app_number] => 10300526 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/300526
Clock's out-of-synchronism state detection circuit and optical receiving device using the same Nov 20, 2002 Issued
Array ( [id] => 6667060 [patent_doc_number] => 20030112043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'PLL circuit and control method for PLL circuit' [patent_app_type] => new [patent_app_number] => 10/298822 [patent_app_country] => US [patent_app_date] => 2002-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3993 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20030112043.pdf [firstpage_image] =>[orig_patent_app_number] => 10298822 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/298822
PLL circuit and control method for PLL circuit Nov 18, 2002 Abandoned
Array ( [id] => 1074252 [patent_doc_number] => 06838918 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-04 [patent_title] => 'Hard phase alignment of clock signals using asynchronous level-mode state machine' [patent_app_type] => utility [patent_app_number] => 10/300446 [patent_app_country] => US [patent_app_date] => 2002-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7270 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/838/06838918.pdf [firstpage_image] =>[orig_patent_app_number] => 10300446 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/300446
Hard phase alignment of clock signals using asynchronous level-mode state machine Nov 18, 2002 Issued
Array ( [id] => 1086838 [patent_doc_number] => 06831496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-14 [patent_title] => 'Error correcting latch' [patent_app_type] => B2 [patent_app_number] => 10/299461 [patent_app_country] => US [patent_app_date] => 2002-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 3751 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/831/06831496.pdf [firstpage_image] =>[orig_patent_app_number] => 10299461 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/299461
Error correcting latch Nov 18, 2002 Issued
Array ( [id] => 6786100 [patent_doc_number] => 20030137339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-24 [patent_title] => 'Switching device provided with integrated test means' [patent_app_type] => new [patent_app_number] => 10/299276 [patent_app_country] => US [patent_app_date] => 2002-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2210 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20030137339.pdf [firstpage_image] =>[orig_patent_app_number] => 10299276 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/299276
Switching device provided with integrated test means Nov 18, 2002 Issued
Array ( [id] => 6667065 [patent_doc_number] => 20030112048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'Pulse generator circuit and corresponding micro-electronic component' [patent_app_type] => new [patent_app_number] => 10/298250 [patent_app_country] => US [patent_app_date] => 2002-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2046 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20030112048.pdf [firstpage_image] =>[orig_patent_app_number] => 10298250 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/298250
Pulse generator circuit and corresponding micro-electronic component Nov 14, 2002 Abandoned
Array ( [id] => 7632516 [patent_doc_number] => 06664818 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-16 [patent_title] => 'Current controlled sigmoid neural circuit' [patent_app_type] => B1 [patent_app_number] => 10/292441 [patent_app_country] => US [patent_app_date] => 2002-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2266 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 8 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/664/06664818.pdf [firstpage_image] =>[orig_patent_app_number] => 10292441 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/292441
Current controlled sigmoid neural circuit Nov 12, 2002 Issued
Array ( [id] => 985956 [patent_doc_number] => 06924690 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-02 [patent_title] => 'Voltage switching circuit' [patent_app_type] => utility [patent_app_number] => 10/292527 [patent_app_country] => US [patent_app_date] => 2002-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 7350 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/924/06924690.pdf [firstpage_image] =>[orig_patent_app_number] => 10292527 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/292527
Voltage switching circuit Nov 12, 2002 Issued
Array ( [id] => 1137517 [patent_doc_number] => 06784699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-31 [patent_title] => 'Glitch free clock multiplexing circuit with asynchronous switch control and minimum switch over time' [patent_app_type] => B2 [patent_app_number] => 10/292243 [patent_app_country] => US [patent_app_date] => 2002-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2104 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/784/06784699.pdf [firstpage_image] =>[orig_patent_app_number] => 10292243 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/292243
Glitch free clock multiplexing circuit with asynchronous switch control and minimum switch over time Nov 11, 2002 Issued
Array ( [id] => 1249285 [patent_doc_number] => 06674309 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'Differential time sampling circuit' [patent_app_type] => B1 [patent_app_number] => 10/292114 [patent_app_country] => US [patent_app_date] => 2002-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6008 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/674/06674309.pdf [firstpage_image] =>[orig_patent_app_number] => 10292114 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/292114
Differential time sampling circuit Nov 11, 2002 Issued
Array ( [id] => 7355560 [patent_doc_number] => 20040090257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'LOW POWER OVERDRIVEN PASS GATE LATCH' [patent_app_type] => new [patent_app_number] => 10/290636 [patent_app_country] => US [patent_app_date] => 2002-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1149 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20040090257.pdf [firstpage_image] =>[orig_patent_app_number] => 10290636 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/290636
Low power overdriven pass gate latch Nov 7, 2002 Issued
Array ( [id] => 7632499 [patent_doc_number] => 06664835 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-16 [patent_title] => 'Phase splitter' [patent_app_type] => B1 [patent_app_number] => 10/289359 [patent_app_country] => US [patent_app_date] => 2002-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2551 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/664/06664835.pdf [firstpage_image] =>[orig_patent_app_number] => 10289359 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/289359
Phase splitter Nov 6, 2002 Issued
Array ( [id] => 1254876 [patent_doc_number] => 06670838 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-30 [patent_title] => 'Digital clock adaptive duty cycle circuit' [patent_app_type] => B1 [patent_app_number] => 10/288786 [patent_app_country] => US [patent_app_date] => 2002-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 3883 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/670/06670838.pdf [firstpage_image] =>[orig_patent_app_number] => 10288786 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/288786
Digital clock adaptive duty cycle circuit Nov 4, 2002 Issued
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