My Trang Ton

Array ( [id] => 6799810 [patent_doc_number] => 20030094974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-22 [patent_title] => 'Clock\'s out-of-synchronism state detection circuit and optical receiving device using the same' [patent_app_type] => new [patent_app_number] => 10/300526 [patent_app_country] => US [patent_app_date] => 2002-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3874 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20030094974.pdf [firstpage_image] =>[orig_patent_app_number] => 10300526 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1086838 [patent_doc_number] => 06831496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-14 [patent_title] => 'Error correcting latch' [patent_app_type] => B2 [patent_app_number] => 10/299461 [patent_app_country] => US [patent_app_date] => 2002-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 3751 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/831/06831496.pdf [firstpage_image] =>[orig_patent_app_number] => 10299461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6667060 [patent_doc_number] => 20030112043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'PLL circuit and control method for PLL circuit' [patent_app_type] => new [patent_app_number] => 10/298822 [patent_app_country] => US [patent_app_date] => 2002-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3993 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20030112043.pdf [firstpage_image] =>[orig_patent_app_number] => 10298822 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1074252 [patent_doc_number] => 06838918 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-04 [patent_title] => 'Hard phase alignment of clock signals using asynchronous level-mode state machine' [patent_app_type] => utility [patent_app_number] => 10/300446 [patent_app_country] => US [patent_app_date] => 2002-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7270 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/838/06838918.pdf [firstpage_image] =>[orig_patent_app_number] => 10300446 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6786100 [patent_doc_number] => 20030137339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-24 [patent_title] => 'Switching device provided with integrated test means' [patent_app_type] => new [patent_app_number] => 10/299276 [patent_app_country] => US [patent_app_date] => 2002-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2210 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20030137339.pdf [firstpage_image] =>[orig_patent_app_number] => 10299276 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6667065 [patent_doc_number] => 20030112048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'Pulse generator circuit and corresponding micro-electronic component' [patent_app_type] => new [patent_app_number] => 10/298250 [patent_app_country] => US [patent_app_date] => 2002-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2046 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20030112048.pdf [firstpage_image] =>[orig_patent_app_number] => 10298250 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7632516 [patent_doc_number] => 06664818 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-16 [patent_title] => 'Current controlled sigmoid neural circuit' [patent_app_type] => B1 [patent_app_number] => 10/292441 [patent_app_country] => US [patent_app_date] => 2002-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2266 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 8 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/664/06664818.pdf [firstpage_image] =>[orig_patent_app_number] => 10292441 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 985956 [patent_doc_number] => 06924690 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-02 [patent_title] => 'Voltage switching circuit' [patent_app_type] => utility [patent_app_number] => 10/292527 [patent_app_country] => US [patent_app_date] => 2002-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 7350 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/924/06924690.pdf [firstpage_image] =>[orig_patent_app_number] => 10292527 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1137517 [patent_doc_number] => 06784699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-31 [patent_title] => 'Glitch free clock multiplexing circuit with asynchronous switch control and minimum switch over time' [patent_app_type] => B2 [patent_app_number] => 10/292243 [patent_app_country] => US [patent_app_date] => 2002-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2104 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/784/06784699.pdf [firstpage_image] =>[orig_patent_app_number] => 10292243 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1249285 [patent_doc_number] => 06674309 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'Differential time sampling circuit' [patent_app_type] => B1 [patent_app_number] => 10/292114 [patent_app_country] => US [patent_app_date] => 2002-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6008 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/674/06674309.pdf [firstpage_image] =>[orig_patent_app_number] => 10292114 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7355560 [patent_doc_number] => 20040090257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'LOW POWER OVERDRIVEN PASS GATE LATCH' [patent_app_type] => new [patent_app_number] => 10/290636 [patent_app_country] => US [patent_app_date] => 2002-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1149 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20040090257.pdf [firstpage_image] =>[orig_patent_app_number] => 10290636 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7632499 [patent_doc_number] => 06664835 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-16 [patent_title] => 'Phase splitter' [patent_app_type] => B1 [patent_app_number] => 10/289359 [patent_app_country] => US [patent_app_date] => 2002-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2551 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/664/06664835.pdf [firstpage_image] =>[orig_patent_app_number] => 10289359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1254876 [patent_doc_number] => 06670838 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-30 [patent_title] => 'Digital clock adaptive duty cycle circuit' [patent_app_type] => B1 [patent_app_number] => 10/288786 [patent_app_country] => US [patent_app_date] => 2002-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 3883 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/670/06670838.pdf [firstpage_image] =>[orig_patent_app_number] => 10288786 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1222450 [patent_doc_number] => 06703877 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-09 [patent_title] => 'Clock shaping circuit and electronic equipment' [patent_app_type] => B2 [patent_app_number] => 10/286418 [patent_app_country] => US [patent_app_date] => 2002-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 14104 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/703/06703877.pdf [firstpage_image] =>[orig_patent_app_number] => 10286418 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1069601 [patent_doc_number] => 06844762 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-18 [patent_title] => 'Capacitive charge pump' [patent_app_type] => utility [patent_app_number] => 10/283869 [patent_app_country] => US [patent_app_date] => 2002-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7184 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/844/06844762.pdf [firstpage_image] =>[orig_patent_app_number] => 10283869 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1311971 [patent_doc_number] => 06617905 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-09 [patent_title] => 'System and method for threshold bias offset voltage cancellation in a comparator' [patent_app_type] => B1 [patent_app_number] => 10/282547 [patent_app_country] => US [patent_app_date] => 2002-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3320 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/617/06617905.pdf [firstpage_image] =>[orig_patent_app_number] => 10282547 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1121595 [patent_doc_number] => 06798252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-28 [patent_title] => 'High speed sense amplifier' [patent_app_type] => B2 [patent_app_number] => 10/110173 [patent_app_country] => US [patent_app_date] => 2002-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4796 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/798/06798252.pdf [firstpage_image] =>[orig_patent_app_number] => 10110173 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1289664 [patent_doc_number] => 06639449 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-28 [patent_title] => 'Asynchronous glitch-free clock multiplexer' [patent_app_type] => B1 [patent_app_number] => 10/278415 [patent_app_country] => US [patent_app_date] => 2002-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4719 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/639/06639449.pdf [firstpage_image] =>[orig_patent_app_number] => 10278415 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6748441 [patent_doc_number] => 20030042961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Variable delay circuit and method, and delay locked loop, memory device and computer system using same' [patent_app_type] => new [patent_app_number] => 10/272279 [patent_app_country] => US [patent_app_date] => 2002-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5682 [patent_no_of_claims] => 77 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20030042961.pdf [firstpage_image] =>[orig_patent_app_number] => 10272279 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7207197 [patent_doc_number] => 20040070438 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-15 [patent_title] => 'Limiter' [patent_app_type] => new [patent_app_number] => 10/270429 [patent_app_country] => US [patent_app_date] => 2002-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2210 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20040070438.pdf [firstpage_image] =>[orig_patent_app_number] => 10270429 [rel_patent_id] =>[rel_patent_doc_number] =>)