
My Trang Ton
Examiner (ID: 3916, Phone: (571)272-1754 , Office: P/3992 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 3992, 2816, 2504 |
| Total Applications | 1512 |
| Issued Applications | 1345 |
| Pending Applications | 95 |
| Abandoned Applications | 73 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6812122
[patent_doc_number] => 20030071672
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-04-17
[patent_title] => 'Clamp circuit for a semiconductor integrated circuit device'
[patent_app_type] => new
[patent_app_number] => 10/270808
[patent_app_country] => US
[patent_app_date] => 2002-10-14
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[patent_figures_cnt] => 10
[patent_no_of_words] => 7616
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[pdf_file] => publications/A1/0071/20030071672.pdf
[firstpage_image] =>[orig_patent_app_number] => 10270808
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/270808 | Clamp circuit for a semiconductor integrated circuit device | Oct 13, 2002 | Issued |
Array
(
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[patent_doc_number] => 06670841
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-12-30
[patent_title] => 'Level shifting circuit'
[patent_app_type] => B2
[patent_app_number] => 10/267666
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[firstpage_image] =>[orig_patent_app_number] => 10267666
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/267666 | Level shifting circuit | Oct 9, 2002 | Issued |
Array
(
[id] => 6748431
[patent_doc_number] => 20030042951
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-03-06
[patent_title] => 'Variable delay circuit and method, and delay locked loop, memory device and computer system using same'
[patent_app_type] => new
[patent_app_number] => 10/268225
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[patent_app_date] => 2002-10-09
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[firstpage_image] =>[orig_patent_app_number] => 10268225
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/268225 | Variable delay circuit and method, and delay locked loop, memory device and computer system using same | Oct 8, 2002 | Issued |
Array
(
[id] => 1303555
[patent_doc_number] => 06624682
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-23
[patent_title] => 'Method and an apparatus to actively sink current in an integrated circuit with a floating I/O supply voltage'
[patent_app_type] => B1
[patent_app_number] => 10/267563
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 10267563
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/267563 | Method and an apparatus to actively sink current in an integrated circuit with a floating I/O supply voltage | Oct 8, 2002 | Issued |
Array
(
[id] => 7632512
[patent_doc_number] => 06664822
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[patent_kind] => B2
[patent_issue_date] => 2003-12-16
[patent_title] => 'Driving device having dummy circuit'
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[pdf_file] => patents/06/664/06664822.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/265685 | Driving device having dummy circuit | Oct 7, 2002 | Issued |
Array
(
[id] => 1289596
[patent_doc_number] => 06639434
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-10-28
[patent_title] => 'Low voltage differential signaling systems and methods'
[patent_app_type] => B1
[patent_app_number] => 10/266361
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[firstpage_image] =>[orig_patent_app_number] => 10266361
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/266361 | Low voltage differential signaling systems and methods | Oct 6, 2002 | Issued |
Array
(
[id] => 1081691
[patent_doc_number] => 06836168
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-12-28
[patent_title] => 'Line driver with programmable slew rates'
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[patent_app_number] => 10/264204
[patent_app_country] => US
[patent_app_date] => 2002-10-02
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[pdf_file] => patents/06/836/06836168.pdf
[firstpage_image] =>[orig_patent_app_number] => 10264204
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/264204 | Line driver with programmable slew rates | Oct 1, 2002 | Issued |
Array
(
[id] => 1222440
[patent_doc_number] => 06703873
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-09
[patent_title] => 'Pull-up circuit for input/output terminals of electronic appliances'
[patent_app_type] => B2
[patent_app_number] => 10/263337
[patent_app_country] => US
[patent_app_date] => 2002-10-01
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/263337 | Pull-up circuit for input/output terminals of electronic appliances | Sep 30, 2002 | Issued |
Array
(
[id] => 6837465
[patent_doc_number] => 20030034805
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-02-20
[patent_title] => 'Regenerative signal level converter'
[patent_app_type] => new
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[firstpage_image] =>[orig_patent_app_number] => 10263259
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/263259 | Regenerative signal level converter | Sep 30, 2002 | Abandoned |
Array
(
[id] => 1277981
[patent_doc_number] => 06650168
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-11-18
[patent_title] => 'High-speed level shifter using zero-threshold MOSFETS'
[patent_app_type] => B1
[patent_app_number] => 10/261344
[patent_app_country] => US
[patent_app_date] => 2002-09-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/261344 | High-speed level shifter using zero-threshold MOSFETS | Sep 29, 2002 | Issued |
Array
(
[id] => 1159926
[patent_doc_number] => 06765423
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-07-20
[patent_title] => 'Semiconductor circuit having clock synchronous receiver circuit'
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[pdf_file] => patents/06/765/06765423.pdf
[firstpage_image] =>[orig_patent_app_number] => 10259775
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/259775 | Semiconductor circuit having clock synchronous receiver circuit | Sep 29, 2002 | Issued |
Array
(
[id] => 1064085
[patent_doc_number] => 06850099
[patent_country] => US
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[patent_title] => 'Scalable driver device and related integrated circuit'
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Array
(
[id] => 1207506
[patent_doc_number] => 06717444
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[patent_title] => 'Low power latch sense amplifier'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/259489 | Low power latch sense amplifier | Sep 29, 2002 | Issued |
Array
(
[id] => 1182895
[patent_doc_number] => 06741112
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[patent_kind] => B2
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[patent_title] => 'Input circuit with hysteresis'
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[pdf_file] => patents/06/741/06741112.pdf
[firstpage_image] =>[orig_patent_app_number] => 10255577
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/255577 | Input circuit with hysteresis | Sep 26, 2002 | Issued |
Array
(
[id] => 7268182
[patent_doc_number] => 20040056700
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-25
[patent_title] => 'SSTL PULL-DOWN PRE-DRIVER DESIGN USING REGULATED POWER SUPPLY'
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[patent_app_number] => 10/247127
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/247127 | SSTL pull-down pre-driver design using regulated power supply | Sep 18, 2002 | Issued |
Array
(
[id] => 1177074
[patent_doc_number] => 06750688
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-06-15
[patent_title] => 'Semiconductor integrated circuit device and delay-locked loop device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/242067 | Semiconductor integrated circuit device and delay-locked loop device | Sep 11, 2002 | Issued |
Array
(
[id] => 6753881
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[patent_title] => 'LED lamp package for packaging an LED driver with an LED'
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Array
(
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Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/223282 | Controlled rise time output driver | Aug 18, 2002 | Issued |