My Trang Ton

Array ( [id] => 1394758 [patent_doc_number] => 06552578 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Power down circuit detecting duty cycle of input signal' [patent_app_type] => B1 [patent_app_number] => 10/064082 [patent_app_country] => US [patent_app_date] => 2002-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2374 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/552/06552578.pdf [firstpage_image] =>[orig_patent_app_number] => 10064082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1389756 [patent_doc_number] => 06556060 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Latch structures and systems with enhanced speed and reduced current drain' [patent_app_type] => B1 [patent_app_number] => 10/166220 [patent_app_country] => US [patent_app_date] => 2002-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2212 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/556/06556060.pdf [firstpage_image] =>[orig_patent_app_number] => 10166220 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1233112 [patent_doc_number] => 06693479 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-17 [patent_title] => 'Boost structures for switched-capacitor systems' [patent_app_type] => B1 [patent_app_number] => 10/165681 [patent_app_country] => US [patent_app_date] => 2002-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2745 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/693/06693479.pdf [firstpage_image] =>[orig_patent_app_number] => 10165681 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7963605 [patent_doc_number] => 06680626 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-20 [patent_title] => 'High speed differential receiver' [patent_app_type] => B2 [patent_app_number] => 10/161931 [patent_app_country] => US [patent_app_date] => 2002-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1894 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/680/06680626.pdf [firstpage_image] =>[orig_patent_app_number] => 10161931 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1331762 [patent_doc_number] => 06600348 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'Input/output device having dynamic delay' [patent_app_type] => B1 [patent_app_number] => 10/159881 [patent_app_country] => US [patent_app_date] => 2002-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 9879 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/600/06600348.pdf [firstpage_image] =>[orig_patent_app_number] => 10159881 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6417902 [patent_doc_number] => 20020125917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Method of making an electrically programmable' [patent_app_type] => new [patent_app_number] => 10/143417 [patent_app_country] => US [patent_app_date] => 2002-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6315 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20020125917.pdf [firstpage_image] =>[orig_patent_app_number] => 10143417 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7623377 [patent_doc_number] => 06686788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-03 [patent_title] => 'Delay circuit of clock synchronization device using delay cells having wide delay range' [patent_app_type] => B2 [patent_app_number] => 10/140280 [patent_app_country] => US [patent_app_date] => 2002-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3928 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/686/06686788.pdf [firstpage_image] =>[orig_patent_app_number] => 10140280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1387585 [patent_doc_number] => 06559693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-06 [patent_title] => 'Integrated circuit designs for high speed signal processing' [patent_app_type] => B2 [patent_app_number] => 10/137988 [patent_app_country] => US [patent_app_date] => 2002-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 4677 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/559/06559693.pdf [firstpage_image] =>[orig_patent_app_number] => 10137988 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1025850 [patent_doc_number] => 06885224 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-26 [patent_title] => 'Apparatus for comparing an input voltage with a threshold voltage' [patent_app_type] => utility [patent_app_number] => 10/126826 [patent_app_country] => US [patent_app_date] => 2002-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4551 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/885/06885224.pdf [firstpage_image] =>[orig_patent_app_number] => 10126826 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1389692 [patent_doc_number] => 06556056 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Method and apparatus for using parasitic effects in processing high speed signals' [patent_app_type] => B1 [patent_app_number] => 10/118733 [patent_app_country] => US [patent_app_date] => 2002-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 6043 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/556/06556056.pdf [firstpage_image] =>[orig_patent_app_number] => 10118733 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7329771 [patent_doc_number] => 20040130363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-08 [patent_title] => 'Storing an unchanging binary code in an integrated circuit' [patent_app_type] => new [patent_app_number] => 10/473057 [patent_app_country] => US [patent_app_date] => 2004-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2973 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20040130363.pdf [firstpage_image] =>[orig_patent_app_number] => 10473057 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1241663 [patent_doc_number] => 06683486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-27 [patent_title] => 'Low voltage shifter with latching function' [patent_app_type] => B2 [patent_app_number] => 10/114221 [patent_app_country] => US [patent_app_date] => 2002-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2967 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/683/06683486.pdf [firstpage_image] =>[orig_patent_app_number] => 10114221 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6368486 [patent_doc_number] => 20020118053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-29 [patent_title] => 'PLL device' [patent_app_type] => new [patent_app_number] => 10/107553 [patent_app_country] => US [patent_app_date] => 2002-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 22721 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20020118053.pdf [firstpage_image] =>[orig_patent_app_number] => 10107553 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1469064 [patent_doc_number] => 06459308 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Method and system design with systematic adjustment of individual building blocks for high speed bipolar circuits' [patent_app_type] => B1 [patent_app_number] => 10/107946 [patent_app_country] => US [patent_app_date] => 2002-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 6751 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/459/06459308.pdf [firstpage_image] =>[orig_patent_app_number] => 10107946 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1367248 [patent_doc_number] => 06573774 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-03 [patent_title] => 'Error correcting latch' [patent_app_type] => B1 [patent_app_number] => 10/107293 [patent_app_country] => US [patent_app_date] => 2002-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 3773 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/573/06573774.pdf [firstpage_image] =>[orig_patent_app_number] => 10107293 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6799824 [patent_doc_number] => 20030094988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-22 [patent_title] => 'Voltage generating circuit, level shift circuit and semiconductor device' [patent_app_type] => new [patent_app_number] => 10/103761 [patent_app_country] => US [patent_app_date] => 2002-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5775 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20030094988.pdf [firstpage_image] =>[orig_patent_app_number] => 10103761 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6827959 [patent_doc_number] => 20030179017 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'MEASURING POWER SUPPLY STABILITY' [patent_app_type] => new [patent_app_number] => 10/104393 [patent_app_country] => US [patent_app_date] => 2002-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4865 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20030179017.pdf [firstpage_image] =>[orig_patent_app_number] => 10104393 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1312009 [patent_doc_number] => 06617908 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-09 [patent_title] => 'Switched-capacitor circuits with reduced distortion' [patent_app_type] => B1 [patent_app_number] => 10/104125 [patent_app_country] => US [patent_app_date] => 2002-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2536 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/617/06617908.pdf [firstpage_image] =>[orig_patent_app_number] => 10104125 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1338375 [patent_doc_number] => 06597225 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'Data capture circuit with series channel sampling structure' [patent_app_type] => B1 [patent_app_number] => 10/104248 [patent_app_country] => US [patent_app_date] => 2002-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5803 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/597/06597225.pdf [firstpage_image] =>[orig_patent_app_number] => 10104248 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5783512 [patent_doc_number] => 20020158674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-31 [patent_title] => 'Dynamic termination logic driver with improved impedance control' [patent_app_type] => new [patent_app_number] => 10/102564 [patent_app_country] => US [patent_app_date] => 2002-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 16565 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20020158674.pdf [firstpage_image] =>[orig_patent_app_number] => 10102564 [rel_patent_id] =>[rel_patent_doc_number] =>)