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Examiner (ID: 3916, Phone: (571)272-1754 , Office: P/3992 )

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2504
Total Applications
1512
Issued Applications
1345
Pending Applications
95
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1519560 [patent_doc_number] => 06501314 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Programmable differential D flip-flop' [patent_app_type] => B1 [patent_app_number] => 10/092246 [patent_app_country] => US [patent_app_date] => 2002-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2580 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/501/06501314.pdf [firstpage_image] =>[orig_patent_app_number] => 10092246 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/092246
Programmable differential D flip-flop Mar 5, 2002 Issued
Array ( [id] => 6447923 [patent_doc_number] => 20020149405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-17 [patent_title] => 'Semiconductor integrated circuit device including a clock synchronous type logical processing circuit' [patent_app_type] => new [patent_app_number] => 10/086874 [patent_app_country] => US [patent_app_date] => 2002-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 17303 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20020149405.pdf [firstpage_image] =>[orig_patent_app_number] => 10086874 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/086874
Semiconductor integrated circuit device including a clock synchronous type logical processing circuit Mar 3, 2002 Issued
Array ( [id] => 5856921 [patent_doc_number] => 20020121939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-05 [patent_title] => 'Circuit configuration for the compensation of leakage currents in a voltage-controlled oscillator of a PLL circuit' [patent_app_type] => new [patent_app_number] => 10/087299 [patent_app_country] => US [patent_app_date] => 2002-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1490 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20020121939.pdf [firstpage_image] =>[orig_patent_app_number] => 10087299 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/087299
Circuit configuration for the compensation of leakage currents in a voltage-controlled oscillator of a PLL circuit Feb 28, 2002 Issued
Array ( [id] => 6388876 [patent_doc_number] => 20020180498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Direct digital synthesizer phase locked loop' [patent_app_type] => new [patent_app_number] => 10/087521 [patent_app_country] => US [patent_app_date] => 2002-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6748 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20020180498.pdf [firstpage_image] =>[orig_patent_app_number] => 10087521 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/087521
Direct digital synthesizer phase locked loop Feb 28, 2002 Issued
Array ( [id] => 6457469 [patent_doc_number] => 20020150172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-17 [patent_title] => 'Caller-ID demodulation apparatus and method using multiple thresholds' [patent_app_type] => new [patent_app_number] => 10/086787 [patent_app_country] => US [patent_app_date] => 2002-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9917 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20020150172.pdf [firstpage_image] =>[orig_patent_app_number] => 10086787 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/086787
Caller-ID demodulation apparatus and method using multiple thresholds Feb 28, 2002 Issued
Array ( [id] => 5901930 [patent_doc_number] => 20020140470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'Mode switching method for PLL circuit and mode control circuit for PLL circuit' [patent_app_type] => new [patent_app_number] => 10/084974 [patent_app_country] => US [patent_app_date] => 2002-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6749 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20020140470.pdf [firstpage_image] =>[orig_patent_app_number] => 10084974 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/084974
Mode switching method for PLL circuit and mode control circuit for PLL circuit Feb 28, 2002 Issued
Array ( [id] => 6418194 [patent_doc_number] => 20020125958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Dual-band oscillator for preventing reduction in oscillation power caused by bias resistor' [patent_app_type] => new [patent_app_number] => 10/087313 [patent_app_country] => US [patent_app_date] => 2002-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2628 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20020125958.pdf [firstpage_image] =>[orig_patent_app_number] => 10087313 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/087313
Dual-band oscillator for preventing reduction in oscillation power caused by bias resistor Feb 28, 2002 Issued
Array ( [id] => 1247008 [patent_doc_number] => 06677827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-13 [patent_title] => 'Temperature compensated crystal oscillator and method for adjusting output frequency thereof' [patent_app_type] => B2 [patent_app_number] => 10/083404 [patent_app_country] => US [patent_app_date] => 2002-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3765 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/677/06677827.pdf [firstpage_image] =>[orig_patent_app_number] => 10083404 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/083404
Temperature compensated crystal oscillator and method for adjusting output frequency thereof Feb 26, 2002 Issued
Array ( [id] => 1378561 [patent_doc_number] => 06566967 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Configurable triple phase-locked loop circuit and method' [patent_app_type] => B1 [patent_app_number] => 10/085458 [patent_app_country] => US [patent_app_date] => 2002-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3380 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/566/06566967.pdf [firstpage_image] =>[orig_patent_app_number] => 10085458 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/085458
Configurable triple phase-locked loop circuit and method Feb 25, 2002 Issued
Array ( [id] => 7144717 [patent_doc_number] => 20040169547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-02 [patent_title] => 'Electronic circuits' [patent_app_type] => new [patent_app_number] => 10/466697 [patent_app_country] => US [patent_app_date] => 2004-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4341 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20040169547.pdf [firstpage_image] =>[orig_patent_app_number] => 10466697 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/466697
Electronic circuits Feb 25, 2002 Issued
Array ( [id] => 5918711 [patent_doc_number] => 20020113631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Charge pump and PLL' [patent_app_type] => new [patent_app_number] => 10/078144 [patent_app_country] => US [patent_app_date] => 2002-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7106 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20020113631.pdf [firstpage_image] =>[orig_patent_app_number] => 10078144 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/078144
Charge pump and PLL Feb 18, 2002 Issued
Array ( [id] => 1273679 [patent_doc_number] => 06653871 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-25 [patent_title] => 'Method of and circuit for controlling a clock' [patent_app_type] => B2 [patent_app_number] => 10/073490 [patent_app_country] => US [patent_app_date] => 2002-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6001 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/653/06653871.pdf [firstpage_image] =>[orig_patent_app_number] => 10073490 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/073490
Method of and circuit for controlling a clock Feb 12, 2002 Issued
Array ( [id] => 1403089 [patent_doc_number] => 06545508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-08 [patent_title] => 'Detection of clock signal period abnormalities' [patent_app_type] => B2 [patent_app_number] => 10/066508 [patent_app_country] => US [patent_app_date] => 2002-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2507 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/545/06545508.pdf [firstpage_image] =>[orig_patent_app_number] => 10066508 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/066508
Detection of clock signal period abnormalities Jan 30, 2002 Issued
Array ( [id] => 6525505 [patent_doc_number] => 20020109417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-15 [patent_title] => 'Driver circuit for soft turning on a power element connected to an inductive load' [patent_app_type] => new [patent_app_number] => 10/050595 [patent_app_country] => US [patent_app_date] => 2002-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4498 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20020109417.pdf [firstpage_image] =>[orig_patent_app_number] => 10050595 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/050595
Driver circuit for soft turning on a power element connected to an inductive load Jan 14, 2002 Issued
Array ( [id] => 1342191 [patent_doc_number] => 06593793 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'Electronic package with integrated clock distribution structure' [patent_app_type] => B1 [patent_app_number] => 10/042273 [patent_app_country] => US [patent_app_date] => 2002-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 1784 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/593/06593793.pdf [firstpage_image] =>[orig_patent_app_number] => 10042273 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/042273
Electronic package with integrated clock distribution structure Jan 10, 2002 Issued
Array ( [id] => 1387924 [patent_doc_number] => 06559712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method and device for the generation of a random signal with controlled histogram and spectrum' [patent_app_type] => B2 [patent_app_number] => 10/042199 [patent_app_country] => US [patent_app_date] => 2002-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3602 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/559/06559712.pdf [firstpage_image] =>[orig_patent_app_number] => 10042199 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/042199
Method and device for the generation of a random signal with controlled histogram and spectrum Jan 10, 2002 Issued
Array ( [id] => 6368481 [patent_doc_number] => 20020118052 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-29 [patent_title] => 'Differential charge pump circuit' [patent_app_type] => new [patent_app_number] => 10/041490 [patent_app_country] => US [patent_app_date] => 2002-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2648 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20020118052.pdf [firstpage_image] =>[orig_patent_app_number] => 10041490 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/041490
Differential charge pump circuit Jan 9, 2002 Abandoned
Array ( [id] => 6388881 [patent_doc_number] => 20020180499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Method for generating internal clock of semiconductor memory device and circuit thereof' [patent_app_type] => new [patent_app_number] => 10/041091 [patent_app_country] => US [patent_app_date] => 2002-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4183 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20020180499.pdf [firstpage_image] =>[orig_patent_app_number] => 10041091 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/041091
Method for generating internal clock of semiconductor memory device and circuit thereof Jan 6, 2002 Issued
Array ( [id] => 1383010 [patent_doc_number] => 06563359 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-13 [patent_title] => 'Semiconductor integrated circuit including clock modulation circuit' [patent_app_type] => B2 [patent_app_number] => 10/033798 [patent_app_country] => US [patent_app_date] => 2002-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5031 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/563/06563359.pdf [firstpage_image] =>[orig_patent_app_number] => 10033798 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/033798
Semiconductor integrated circuit including clock modulation circuit Jan 2, 2002 Issued
Array ( [id] => 1407056 [patent_doc_number] => 06542013 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-01 [patent_title] => 'Fractional divisors for multiple-phase PLL systems' [patent_app_type] => B1 [patent_app_number] => 10/037915 [patent_app_country] => US [patent_app_date] => 2002-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3941 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/542/06542013.pdf [firstpage_image] =>[orig_patent_app_number] => 10037915 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/037915
Fractional divisors for multiple-phase PLL systems Jan 1, 2002 Issued
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